L1 Cache Pixel Mapping for ALU-Centric GPU Convolution
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Solution Overview
Problem
Current GPU architectures face inefficiencies in performing convolution operations due to reliance on shared memory for pixel data, which increases power consumption and reduces operation speed.
Innovation Solution
The implementation of a GPU with a Level 1 (L1) cache that loads pixels into a General Purpose Register (GPR) using a pixel mapping, independent of filter size, and an Arithmetic Logic Unit (ALU) that stores pixels in a sliding window cache instead of shared memory, eliminating the need for shared memory operations and reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If pixels are loaded into shared memory for convolution operations, then data accessibility is improved, but power consumption increases and operation speed decreases
Solution Approach 1:
The patent extracts pixel data loading operations from shared memory and relocates them to the L1 cache. The L1 cache loads pixels directly into the GPR using pixel mapping, eliminating the need for shared memory operations. This extraction of the data loading function from shared memory to L1 cache reduces power consumption while maintaining data accessibility for convolution operations.
Solution Approach 2:
The L1 cache acts as an intermediary between external memory and the GPR/ALU system. Instead of loading pixels directly from external memory through shared memory, the L1 cache pre-loads and stores pixel data in its memory pool, then efficiently transfers it to the GPR. This intermediary role reduces the power consumption of memory operations while maintaining fast data access for the ALU.
2Ease of operation
If pixels are loaded into shared memory for convolution operations, then data accessibility is improved, but operation speed decreases
Solution Approach 1:
The patent extracts the pixel loading operation from shared memory to the L1 cache, which provides faster access. The L1 cache loads pixels directly into the GPR using efficient pixel mapping, eliminating the speed bottleneck of shared memory operations. This extraction enables the ALU to access pixel data faster while maintaining full accessibility for convolution operations.
Solution Approach 2:
The L1 cache performs preliminary loading of pixel data into its memory pool before the ALU needs it for convolution operations. By pre-loading and organizing pixel data in the L1 cache with pixel mapping, the system eliminates wait times during ALU operations. This preliminary action ensures that pixel data is readily available in the GPR when the ALU requires it, significantly improving operation speed.
3Device complexity
If shared memory is used for pixel data storage, then hardware design is simplified, but power consumption increases
Solution Approach 1:
The patent extracts the pixel data storage function from shared memory and relocates it to the L1 cache. The L1 cache with its pixel mapping capability handles all pixel data loading and storage needs, eliminating the requirement for shared memory in the convolution operation path. This extraction reduces power consumption while the L1 cache and GPR structure maintains adequate hardware design complexity.
Solution Approach 2:
The L1 cache is designed to serve multiple functions: it acts as both the pixel data storage mechanism and the data transfer intermediary to the GPR. By making the L1 cache universal for both storage and data movement operations, the patent eliminates the need for separate shared memory infrastructure, reducing overall power consumption while maintaining functional capability.
4Ease of operation
If shared memory operations are performed for pixel loading, then data accessibility is maintained, but hardware complexity increases
Solution Approach 1:
The patent extracts shared memory operations from the system and replaces them with L1 cache-based pixel loading. The L1 cache with pixel mapping provides all necessary data accessibility functions that previously required shared memory, eliminating the need for complex shared memory control logic, address translation, and coherence management. This extraction reduces hardware complexity while maintaining full data accessibility for the ALU.
Data Source
AI summary
A GPU comprises: a GPR comprising registers; an L1 cache coupled to the GPR and configured to implement a pixel mapping by: segregating pixels of an image into regions, the regions comprise a first region and a second region, the first region comprises first pixels, and the second region comprises second pixels, loading the first pixels into the GPR in a horizontal manner, and loading the second pixels into the GPR in a vertical manner; and an ALU configured to read the first pixels and the second pixels independently of a shared memory.