Bipolar Decoder for 3D Crosspoint Memory Energy Reduction
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Solution Overview
Problem
The high energy expenditure in decoder addressing for 3D crosspoint memory devices due to the need to switch transistors and change gate biases for selecting and deselecting address lines leads to inefficiencies in memory operations.
Innovation Solution
A bipolar decoder architecture that includes bias circuits with transistors to apply positive, negative, and neutral biases to address lines, avoiding the switching of gate voltages for unselected lines, thereby reducing energy consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If traditional decoder addressing is used to select and deselect address lines, then memory operations can be performed, but energy consumption is high due to switching many transistors and changing gate biases
Solution Approach 1:
The decoder addressing function is segmented into two independent parts: a select decoder that activates only the selected address line, and a deselect decoder that deactivates only the previously selected line. This segmentation allows only the necessary transistors to switch states, reducing overall energy consumption while maintaining memory operation functionality.
Solution Approach 2:
The deselect decoder is prepared in advance to immediately deactivate the previously selected address line when a new selection is made. This preliminary action prevents unnecessary voltage swings and transistor switching on unselected lines, thereby reducing energy consumption without impacting memory operation speed.
2Ease of operation
If multiple transistors switch gate biases to deselect address lines, then address line selection can be achieved, but energy expenditure increases due to CV2 power loss
Solution Approach 1:
The deselect function is extracted from the traditional decoder and implemented as a separate deselect decoder circuit. This extraction ensures that only the minimal necessary transistors switch gate biases during deselection, minimizing the CV2 power loss while maintaining ease of address line selection through the select decoder.
3Reliability
If traditional decoder architecture switches transistors for each address line, then complete address line control is achieved, but energy consumption increases due to voltage swings on all address lines
Solution Approach 1:
The decoder architecture dynamically activates only the necessary components: the select decoder dynamically switches to activate only the currently selected address line, while the deselect decoder dynamically deactivates only the previously selected line. This dynamic operation ensures reliable address line control while minimizing energy consumption by avoiding unnecessary voltage swings on inactive lines.
Data Source
AI summary
A memory device including a memory array and address lines; and decoder circuitry to apply a first bias to a WL coupled to a memory cell selected for a memory operation, a second bias to a BL coupled to the selected memory cell, and one or more neutral biases to the other BLs and WLs of the memory array; wherein the decoder circuitry comprises a plurality of bias circuits coupled to the address lines, a first bias circuit of the plurality of bias circuits comprising a transistor pair and an additional transistor coupled to an address line of the plurality of address lines, wherein the bias circuit is to apply, to the address line, the first bias through the transistor pair in a first state, the second bias through the transistor pair in a second state, and the neutral bias through the additional transistor in a third state.