Built-in Self-Test for Heterogeneous RF Chiplets
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Solution Overview
Problem
Heterogeneous integration of radio frequency (RF) transistor chiplets into a host wafer for electronic assemblies faces challenges in confirming assembly yield and testing transistors efficiently, leading to increased costs and reduced manufacturing efficiency due to the need for pre-assembly testing of separately fabricated microelectronic circuits.
Innovation Solution
Incorporating built-in self-test (BIST) circuitry, including ring oscillators with CMOS transistors and electrical interconnects, within the host wafer and RF transistor chiplets to enable on-chip testing of transistor performance, DC characteristics, gain, linearity, and speed, thereby reducing the need for off-chip testing and improving assembly yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-assembly testing is performed on separately fabricated microelectronic circuits, then assembly yield can be confirmed and transistor performance can be tested, but manufacturing cost increases and manufacturing efficiency decreases
Solution Approach 1:
The patent implements built-in self-test (BIST) circuitry that performs testing functions during the manufacturing process itself, eliminating the need for separate pre-assembly testing steps. The BIST circuitry is integrated into the host wafer and chiplets, enabling automated testing of transistor performance and assembly yield confirmation as part of the fabrication process, thereby reducing additional manufacturing costs while maintaining reliability
Solution Approach 2:
The BIST circuitry enables the system to test itself autonomously during manufacturing. The host wafer contains BIST circuitry that can automatically test the performance of chiplet transistors and confirm assembly yield without requiring external testing equipment or separate testing processes, thereby reducing manufacturing complexity and cost while improving efficiency
2Reliability
If pre-assembly testing is performed on separately fabricated microelectronic circuits, then assembly yield can be confirmed and transistor performance can be tested, but manufacturing efficiency decreases due to increased process steps
Solution Approach 1:
The BIST circuitry is integrated into the host wafer during fabrication, enabling testing to be performed as part of the manufacturing process rather than as a separate subsequent step. This preliminary integration of testing capability allows for continuous manufacturing flow without interruption for separate testing, thereby maintaining high productivity while ensuring assembly yield
Solution Approach 2:
The patent merges the testing function with the manufacturing process by integrating BIST circuitry into the host wafer and chiplets. The BIST circuitry combines testing operations with the fabrication process, allowing transistor performance testing and assembly yield confirmation to occur concurrently with manufacturing activities, thereby eliminating the need for separate testing steps and improving manufacturing efficiency
3Adaptability or versatility
If heterogeneous integration is used to combine microelectronic circuits with different materials and manufacturing processes, then circuit performance increases, but testing and confirming assembly yield becomes more complex
Solution Approach 1:
The BIST circuitry integrated into the host wafer provides universal testing capability that can test multiple types of chiplet transistors fabricated with different materials and processes. The unified BIST interface and testing methodology can accommodate heterogeneous chiplets, simplifying the testing process despite the diversity of integrated circuits and enabling comprehensive performance verification across different technologies
Solution Approach 2:
The BIST circuitry acts as an intermediary between the heterogeneous chiplets and the testing system. The BIST interface on the host wafer provides a standardized method for testing chiplets from different fabrication processes, mediating the complexity of heterogeneous integration by presenting a uniform testing approach that simplifies yield confirmation and performance testing across diverse circuit technologies
Data Source
AI summary
An electronic assembly has a host wafer having a first circuit including wafer transistors and passive, non-transistor devices. Chiplets have a second circuit including at least one radio frequency (RF) transistor device. Electrical interconnects are between the chiplets and wafer. The electrical interconnects electrically connect the first circuit to the second circuits. Oscillators that have the wafer transistor, the RF transistor and the electrical interconnects produce a signal for built-in self-test circuits for testing an assembly design of the electronic assembly and speeds of the RF chiplet transistors.