Backside Illuminated Image Sensor Vertical Capacitor Integration
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Solution Overview
Problem
Backside illuminated image sensors face challenges in achieving compact size while maintaining image quality and stability due to small dimensions and variations in current consumption affecting supply voltage, which can lead to ripple and interference, and require efficient voltage regulation and clock stabilization.
Innovation Solution
The integration of a peripheral circuit with capacitor layers embedded in a dielectric layer for voltage regulation and charge pump operation, where the capacitor layers are electrically connected to the peripheral circuit, allowing for compact design and improved voltage stability and clock generation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the image sensor dimensions are reduced for compact applications, then the sensor can be used in small-scale devices like endoscopes, but the peripheral area for readout circuits becomes extremely limited (less than 100 μm width)
Solution Approach 1:
The patent transitions from planar capacitor placement to three-dimensional vertical stacking of capacitor layers above the pixel array. This allows capacitors to be positioned in the vertical dimension rather than consuming horizontal peripheral area, enabling compact sensor design with sufficient space for voltage regulation circuits.
Solution Approach 2:
The patent integrates multiple functions into the peripheral circuit region, including voltage regulation, charge pump operation, and clock generation, all within the limited peripheral area. The capacitor layers serve both voltage decoupling and charge storage functions for the readout circuits.
2Reliability
If capacitive decoupling is provided for the readout circuitry to improve image quality, then voltage stability improves, but the peripheral area required for circuit integration increases
Solution Approach 1:
The patent places capacitor layers in the vertical dimension above the pixel array rather than in the planar peripheral area. This allows capacitive decoupling to be implemented without increasing the horizontal footprint of the peripheral circuit region.
Solution Approach 2:
The patent combines the voltage regulation function with the capacitor structure by integrating the peripheral circuitry that controls the capacitors directly beneath or adjacent to the capacitor layers, merging voltage regulation and decoupling functions into a compact integrated structure.
3Reliability
If voltage regulation and clock stabilization circuits are integrated in the image sensor to handle current consumption variations, then supply voltage stability and clock signal stability improve, but the device complexity increases
Solution Approach 1:
The patent integrates multiple functions (voltage regulation, charge pump operation, clock generation, and capacitive decoupling) into a single peripheral circuit block. This multi-functional integration provides comprehensive voltage and clock stability while consolidating circuitry into a compact form.
Solution Approach 2:
By positioning capacitor layers vertically above the pixel array and integrating the controlling peripheral circuitry in the same vertical stack, the patent reduces the horizontal spread of complex circuits, making the integrated design more manageable despite the multiple functions performed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables better power decoupling, reducing sensitivity to voltage variations, stabilizing clock signals, and enhancing pixel performance by allowing on-chip voltage regulation and negative voltage generation, resulting in improved image quality and dynamic range.
Implementation Method 1
a first capacitor layer of electrically conductive material embedded in the dielectric layer and a second capacitor layer of electrically conductive material embedded in the dielectric layer at a distance from the first capacitor layer. The first and second capacitor layers form at least one capacitor
Implementation Method 2
a dielectric layer on or above a main surface 10 of the substrate 1
Data Source
Figure 1~2
Figure 3~6
Figure 7~8
AI summary
The backside illuminated image sensor comprises a substrate (1) of semiconductor material, detector elements (11) arranged at a main surface (10), a dielectric layer (3) on or above the main surface (10), a first capacitor layer (7) and a second capacitor layer (8) above the main surface (10), the capacitor layers (7, 8) forming a capacitor (C1, C2). A peripheral circuit (12) is integrated in the substrate (1) apart from the detector elements (11), the peripheral circuit (12) being configured for one or more operations of the group consisting of voltage regulation, charge pump operation and stabilization of clock generation, and the capacitor layers (7, 8) are electrically connected with contact regions (13) of the peripheral circuit (12).