BIST Address Generator for Memory Test Time Reduction
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Solution Overview
Problem
Conventional Built-in Self Test (BIST) circuits in semiconductor integrated circuits require a long time to perform simulations due to the need to generate all addresses for write and read operations, especially in memory devices with a large number of words or multiple memories, leading to inefficiencies in connection testing.
Innovation Solution
The implementation of a BIST circuit with an address generator that operates in two modes: one generating address signals for all addresses and another generating signals such that each bit can be either 0 or 1, reducing the test range to only necessary addresses, thereby shortening the number of steps and time required for the BIST simulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the BIST circuit generates all addresses for write and read operations, then the test coverage is complete, but the simulation time becomes significantly long
Solution Approach 1:
The patent applies partial action by generating only a representative subset of addresses for BIST operations rather than all possible addresses. The address generator creates test patterns that cover critical functionality while omitting redundant address sequences, thereby reducing simulation time while maintaining adequate test coverage for detecting connection failures.
Solution Approach 2:
The address generation process is segmented into multiple independent test patterns. Instead of generating a single comprehensive address sequence covering all addresses, the system divides the testing into several smaller address generation tasks that collectively verify connection integrity without requiring exhaustive address coverage.
2Adaptability or versatility
If the BIST circuit is inserted in a system logic with large number of words or multiple memories, then the test capability is enhanced, but the simulation complexity increases
Solution Approach 1:
The address generator is designed with multi-functionality to handle various memory configurations (different word counts, multiple memory devices) using the same basic circuit structure. By implementing configurable address generation modes and patterns, the BIST circuit adapts to different system complexities without proportionally increasing simulation complexity.
Data Source
AI summary
According to one embodiment, a semiconductor integrated circuit includes at least one memory and at least one built-in self test (BIST) circuit. In the memory, data can be stored. The BIST circuit tests the memory and includes an address generator. The address generator operates in one of a first operating mode and a second operating mode. In the first operating mode, address signals corresponding to all addresses of the memory are generated. In the second operating mode, the address signals are generated such that each bit of an address input of the memory can be one signal state of both 0 and 1 and such that different bits constitute a set of pieces of data in which the bits choose different signal states at least once.