A test system uses multiplexers to route signals from tester pins to device pins.
A semiconductor chip uses a parasitic diode to measure its own temperature during probe testing.
Testing circuit measures effective resistance of discharge element to calibrate discharge interval duration.
Brazing metal members to joint pads on resin boards maintains joint strength across heat cycles while the composite structure prevents warping.
A semiconductor module determines remaining usability by sensing element temperature under predefined electrical load and cooling conditions.
Correction circuits calculate position-based delays to adjust input signals, minimizing skew from parasitic TSV capacitance.
Moving signal sensors perpendicular to scan lines isolates detection circuits and reduces wire interference in dense array substrates.
Virtual entry with scan-controllable storage elements applies transition data to embedded memory read paths.
A probe card analyzer uses a patterned conductive substrate to verify electrical continuity between loop-back probes.
Signal processing apparatus identifies interface modules using detection resistance and voltage changes.
A virtualized I/O device uses a resource discovery table to allocate hardware resources to specific processes.
A printed circuit board testing structure with a dedicated point and grounding element enables accurate radio frequency signal measurement.
A BIST address generator produces selective test patterns to verify memory integrity without exhaustive coverage.
Readiness voting among asynchronous finite state machines prevents synchronization loss and catastrophic failures during state transitions.
A semiconductor test circuit uses input and protection switches to isolate a test transistor from the main circuit during stress voltage application.
Activating a delay component only during burn-in testing resolves timing closure issues without increasing normal operation current consumption.
An encoder selectively forwards capture pulses to specific clock domains during scan testing of integrated circuits.
Segmenting large FPGAs into smaller dies reduces defect probability while maintaining functionality through modular architecture.
A detecting method normalizes temperature rise values to identify abnormal electrical connections in switchgear main circuits.
Integrating a current sense resistor into the semiconductor package eliminates external components and reduces Seebeck effect errors.
A temperature-controlled module uses a fluid chamber and dry air to rapidly cool electronic devices without surface condensation.
A noise measurement system converts time domain signals to frequency domain data using Fast Fourier Transform.
Movable ground blocks in this test jig adapt to lead dimensional variations, ensuring reliable contact without deforming the leads during testing.
Aging test system moves thermal interface material against a heat source to measure conductivity changes.
An API usage tool identifies method calls in source code and compares them against compiled usage guidelines to mark conflicts.
On-chip test control circuitry generates launch and capture pulses via distributed clock dividers to identify delay faults across multiple clock domains.