Distributed Clock Dividers for Delay Fault Testing in Multi-Domain ICs
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Solution Overview
Problem
Integrated circuits with multiple clock domains require comprehensive testing to diagnose delay faults, as existing broadside and delay fault testing methods do not adequately identify the specific issues causing IC failures, especially when measured outputs do not match predicted outputs.
Innovation Solution
An on-chip test control circuitry generates and sends code to distributed clock dividers to control the delay times and types of clock dividers used for launch and capture pulses, enabling precise delay fault testing across clock domains by clocking test data into and out of circuit blocks, and shifting it for evaluation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If broadside testing is used to verify IC operation, then the testing process is simple and quick, but the measurement precision is insufficient to identify specific delay faults
Solution Approach 1:
The patent introduces an intermediary test control circuit that mediates between the test stimulus and the delay fault detection. This circuit generates precise launch and capture clock signals with controlled delay times, enabling accurate delay fault measurement without requiring complex external testing equipment. The intermediary circuit translates simple test inputs into precise timing measurements.
Solution Approach 2:
The testing process is segmented into distinct phases: launch phase, propagation phase, and capture phase. Each phase is controlled by separate clock signals (launch clock, capture clock) with independently controllable delay times. This segmentation allows precise measurement of signal propagation delay through different circuit paths without requiring the entire system to be complex.
2Reliability
If delay fault testing is implemented across multiple clock domains, then the reliability of IC verification is improved, but the device complexity increases due to multiple distributed clock dividers
Solution Approach 1:
The test control circuit is designed with multi-functionality to handle multiple clock domains simultaneously. A single test control circuit can generate and coordinate launch and capture clocks for multiple distributed clock dividers, each operating at different frequencies. This universal approach allows comprehensive delay fault testing across all clock domains without requiring separate dedicated testing circuits for each domain, thus improving reliability while controlling complexity.
Solution Approach 2:
The clock divider ratios and delay times are made dynamically adjustable during testing. The test control circuit can programmatically change the divide ratios of distributed clock dividers and adjust delay times between launch and capture clocks based on the specific clock domain being tested. This dynamic adaptability allows a single flexible testing architecture to reliably test multiple clock domains with different frequency requirements.
3Measurement precision
If precise delay time measurement is achieved through distributed clock dividers, then the measurement precision is improved, but the ease of operation decreases due to complex code sending and control procedures
Solution Approach 1:
The test control circuit incorporates self-service capabilities by automatically generating the necessary control codes and sequences for delay fault testing. Once configured with basic test parameters (clock domain selection, approximate delay range), the circuit autonomously generates launch and capture clock signals, adjusts divider ratios, and coordinates the timing sequences. This self-service approach reduces the operational burden on external testing equipment while maintaining precise delay time measurements.
Solution Approach 2:
The test control circuit uses feedback mechanisms to automatically adjust delay times and clock divider ratios based on preliminary test results. The circuit monitors the propagation of test signals through the circuit under test and automatically fine-tunes the launch and capture clock timing to achieve optimal measurement precision. This feedback-driven operation simplifies the testing process by eliminating manual trial-and-error adjustment while maintaining high measurement precision.
Data Source
AI summary
In an embodiment of the invention, an integrated circuit with several clock domains bank is tested by first disabling a PLL clock and scanning test data into scan chains. Next delay fault testing (DFT) code is transmitted to each distributed clock divider on the integrated circuit. The PLL clock is then enabled to the distributed clock dividers. Selected clock dividers generate launch pulses that allow test data to be propagated from the scan chains into circuit blocks in the clock domains. Capture pulses are then generated by selected distributed clock dividers to capture test data coming form the circuit blocks into the scan chains. Next the PLL clock is disabled and the test data is scanned from the scan chains to an on-chip test control circuit.