Burn-in Testing Circuit Delay Component Activation

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Solution Overview

Problem

Burn-in testing for electronic circuits poses challenges in timing closure due to the need for additional hold time buffers, which increase current consumption and require additional design efforts, as the high voltages used during testing cause timing shifts and hold time violations.

Innovation Solution

A circuit design that includes a signal path with a selectively activatable delay component, which is powered only during burn-in testing and disconnected during normal operation, using a multiplexer and control circuit to manage the delay and prevent current draw when not in use.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If hold time buffers are added to compensate for timing shifts during burn-in testing, then timing requirements are met, but current consumption increases

Engineering Contradiction:
Improvetiming requirement complianceVSAvoidcurrent consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The delay component's activation state is dynamically changed based on operating conditions. During burn-in testing, the delay component is activated to provide hold time compensation. During normal operation, it is deactivated to avoid unnecessary current consumption. This dynamic adaptation resolves the contradiction by making the timing compensation feature conditional rather than permanent.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The supply voltage to the delay component is changed based on the operating mode. A control circuit detects whether the circuit is in burn-in mode or normal operation mode, and accordingly adjusts the voltage supply to the delay component - providing power during burn-in testing and disconnecting power during normal operation. This parameter change enables the delay component to fulfill timing requirements only when needed.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If hold time buffers are added during timing closure, then burn-in corner timing is satisfied, but device complexity increases

Engineering Contradiction:
Improvetiming closure achievementVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The delay component is designed to serve multiple functions: during burn-in testing, it acts as a hold time buffer to satisfy timing requirements; during normal operation, it remains inactive and does not interfere with circuit functionality. The control circuit adds minimal complexity by simply managing the activation state based on operating mode detection.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The timing compensation function is extracted as a separate, independently controllable delay component rather than being integrated into the main circuit paths. This allows the delay component to be selectively activated only during burn-in testing without permanently modifying the normal operation paths, thereby reducing overall device complexity.

Inventive Principle:
Principle #2Taking out (Extraction)

3Reliability

If delay components are permanently integrated into the circuit, then timing is correct during burn-in, but normal operation is significantly influenced

Engineering Contradiction:
Improveburn-in timing correctnessVSAvoidnormal operation performance
Core Design Contradiction:
ReliabilityVSEase of operation

Solution Approach 1:

The delay component's activation state is dynamically changed based on operating conditions. During burn-in testing, the delay component is activated to provide hold time compensation. During normal operation, it is deactivated to avoid unnecessary current consumption. This dynamic adaptation resolves the contradiction by making the timing compensation feature conditional rather than permanent.

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS10180455B2Burn-in testing of circuits
Publication Date: 2019.01.15 INFINEON TECHNOLOGIES AG
  • US10180455B2 patent drawing
  • US10180455B2 patent drawing

AI summary

Circuits and methods are provided for a signal path between circuit parts. During normal operation, a delay is deactivated. During a burn-in test, the delay is activated. In the deactivated state, a delay component may be disconnected from a supply voltage.