Embedded Memory Virtual Entry for Scan Testability
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Solution Overview
Problem
Integrated circuits with embedded memories are not scan testable, which can lead to untested logic circuits and interference with test access, requiring additional circuitry and reducing test efficiency.
Innovation Solution
Incorporating a virtual entry with scan-controllable storage elements in the embedded memory, allowing transition data to be applied to the read path, enabling at-speed testing of logic circuits without adding delay to the read path, thus facilitating full testing of embedded memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If embedded memories are included in integrated circuits, then functional capability is improved, but scan testability deteriorates
Solution Approach 1:
The embedded memory is segmented into functional storage elements and scan-controllable virtual entry elements. This segmentation allows the memory to serve dual purposes: normal operation mode for data storage and test mode for scan testing, thereby resolving the contradiction between functional capability and scan testability.
Solution Approach 2:
The memory structure is made dynamic by introducing mode control logic that can switch between operational mode and test mode. In operational mode, the memory functions as a normal embedded memory; in test mode, the virtual entry becomes scan-controllable, enabling test access without compromising functional capability.
2Adaptability or versatility
If embedded memories are included in integrated circuits, then functional capability is improved, but test access is interfered with
Solution Approach 1:
A virtual entry structure is introduced as an intermediary between the scan chain and the embedded memory. This virtual entry contains scan-controllable storage elements that act as a bridge, allowing test access to logic circuits without interfering with the normal operation of the embedded memory.
Solution Approach 2:
The test access problem is solved by adding a temporal dimension through mode switching. The memory structure operates in different dimensional states: during normal operation, it provides data storage functionality; during testing, it provides scan access functionality through the virtual entry, effectively adding a time-based dimension to resolve the access conflict.
3Reliability
If extra circuitry is added to arrange logic circuits for test access, then test coverage is improved, but device complexity increases
Solution Approach 1:
The virtual entry structure serves multiple functions: it provides scan access during testing, maintains normal memory operation during functional modes, and enables full test coverage of logic circuits. This multi-functionality improves test coverage without requiring separate dedicated test circuitry, thereby avoiding increased device complexity.
Solution Approach 2:
The test access circuitry is merged with the normal memory operation circuitry through the virtual entry structure. The same physical structures serve both testing and operational purposes, eliminating the need for separate extra circuitry and thus improving test coverage without increasing device complexity.
Data Source
AI summary
An integrated circuit. The integrated circuit includes a plurality of logic circuits. The integrated circuit further includes a scan chain including a plurality of scan elements coupled in series, wherein the scan chain is configured to load stimulus data to be applied to the logic circuits for testing. The scan chain is further configured to capture data subsequent to applying the stimulus data. The integrated circuit also includes an embedded memory having a read port, wherein the read port is coupled to one or more of the plurality of logic circuits via a read path. The embedded memory includes a virtual entry having a plurality of scan-controllable storage elements. During testing, the virtual entry is operable to apply transition data to the read path in order to cause logic state transitions in the one or more logic circuits in the read path.