Multi-Chip Module Segmentation for FPGA Yield Optimization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing complexity of circuit designs in FPGAs leads to higher defect rates, resulting in low yield and economic losses for manufacturers, as even localized defects can render entire FPGAs unusable, while defective dies suitable for specific designs are often discarded due to their inability to handle reprogramming requirements.
Innovation Solution
A method of identifying and coupling defective programmable logic devices with functional ones in a multi-chip module, where the defective devices implement fixed portions of a circuit design and the functional devices handle reprogrammable portions, optimizing die usage and reducing costs by reconfiguring defective dies for specific applications.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the area of FPGA die is increased to accommodate more CLBs, IOBs, and routing resources for complex circuit designs, then the functionality and capability of the FPGA is improved, but the probability of defects increases and manufacturing yield decreases
Solution Approach 1:
The patent divides a single large FPGA die into multiple smaller dies, each containing a subset of CLBs, IOBs, and routing resources. This segmentation reduces the defect probability in each individual die while maintaining the overall functionality through modular architecture. Each smaller die can be manufactured with higher yield, and the system achieves adaptability through the combined capability of multiple dies.
2Reliability
If defective FPGAs are discarded to ensure product reliability, then customer satisfaction is maintained, but manufacturing cost increases due to waste of usable dies
Solution Approach 1:
The patent applies local quality by allowing different FPGAs within the same system to have different functional capabilities based on their specific defects. Instead of discarding all defective dies, the system identifies and utilizes FPGAs with localized defects that do not affect specific circuit requirements. This enables differentiated functionality where some FPGAs are optimized for predetermined designs while others are used for reprogrammable applications, reducing waste while maintaining reliability.
Solution Approach 2:
The patent changes the parameter of defect tolerance by introducing a classification system that evaluates the impact of defects on specific circuit designs. Rather than a binary acceptable/rejectable status, the system assigns different operational parameters to FPGAs based on their defect profiles, allowing them to be used for appropriate applications where their limitations do not compromise system reliability.
3Loss of energy
If defective FPGAs are used for predetermined circuit designs, then manufacturing cost is reduced, but the ability to reprogram for revised designs is lost
Solution Approach 1:
The patent segments the FPGA system into multiple independent dies, where some dies are designated for predetermined circuit implementations and others are designated for reprogrammable applications. This segmentation allows the system to simultaneously maintain cost-effectiveness through the use of defective dies for fixed designs while preserving adaptability through dedicated reprogrammable FPGAs that can be reconfigured for revised designs as needed.
Solution Approach 2:
The patent applies local quality by assigning different operational characteristics to different FPGAs within the system. Some FPGAs are optimized for cost-effective predetermined designs with fixed functionality, while other FPGAs are optimized for reprogrammability. This differentiation allows the system to achieve both cost reduction through defective die utilization and adaptability through dedicated reprogrammable components.
Data Source
AI summary
A method of employing a plurality of integrated circuits in a multi-chip module is described. The method comprises steps of identifying a defective programmable logic device implemented on a first die; identifying a functional programmable logic device implemented on a second die; and coupling the defective programmable logic device and the functional programmable logic device. According to an alternate embodiment, a method of employing a plurality of integrated circuits in a multi-chip module comprises steps of configuring a plurality of programmable logic devices on a multi-chip module. A multi-chip integrated circuit package is also described.