BIST Clock Segmentation to Prevent False Test Pass Signals
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Solution Overview
Problem
Built-in self-test (BIST) circuits in semiconductor integrated circuit devices can incorrectly indicate that a test has been conducted, leading to test omissions when the clock line fails, resulting in undetected faults in device-under-test (DUT) circuits.
Innovation Solution
The semiconductor integrated circuit device includes a pattern generator, a result comparator, and a control circuit, where the result comparator has an additional circuit to ensure that a test result signal reflects the actual test status, even if the clock line fails, by using a flip-flop configuration to maintain the test result signal at a high level if the clock line fails, indicating a test failure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the BIST circuit uses a shared clock line for the device-under-test and result comparator, then the device complexity is reduced, but the reliability of test results deteriorates when clock line fails
Solution Approach 1:
The patent segments the clocking system into two independent parts: a first clock signal for the device-under-test and a second clock signal for the BIST circuit operations. This segmentation prevents a single clock line failure from affecting both the device operation and test result generation simultaneously, thereby resolving the contradiction between reduced complexity and maintained reliability.
Solution Approach 2:
The patent introduces an intermediary control mechanism that monitors the test execution status and overrides the test result output when test omission is detected. This intermediary layer ensures that even if the shared clock line fails, the system can prevent incorrect test pass indications by blocking the output of invalid test results.
2Productivity
If the BIST circuit operates with continuous clock signaling, then the productivity of testing is improved, but the risk of undetected faults increases when clock line fails
Solution Approach 1:
The patent implements a feedback mechanism where the control circuit monitors the execution status of test operations and compares it against the expected number of clock cycles. When the actual test execution falls short of the expected cycles (indicating clock line failure), the feedback loop triggers a test omission flag that overrides the test result output, preventing false pass indications while maintaining continuous testing operations.
Solution Approach 2:
The patent performs preliminary validation by tracking the number of clock cycles received during test execution before finalizing the test result. This preliminary action of counting and verifying clock cycle delivery ensures that incomplete tests due to clock line failures are detected and flagged before the test result is output, thereby maintaining fault detection accuracy alongside testing productivity.
3Loss of time
If the test result signal is output immediately after test execution, then the loss of time is reduced, but the manufacturing precision of test results deteriorates when test omission occurs
Solution Approach 1:
The patent performs preliminary validation by tracking the number of clock cycles received during test execution before finalizing the test result. This preliminary action of counting and verifying clock cycle delivery ensures that incomplete tests due to clock line failures are detected and flagged before the test result is output, thereby maintaining fault detection accuracy alongside testing productivity.
Solution Approach 2:
The patent implements a dynamic test result output mechanism that adjusts the timing and validity of test result signals based on real-time monitoring of test execution completeness. The system dynamically determines whether to output a test result or a test omission flag based on the correlation between expected and actual clock cycle counts, ensuring high test result accuracy without significant delay.
Data Source
AI summary
According to one or more embodiments, the semiconductor integrated circuit device includes a pattern generator, a result comparator, and a control circuit. The pattern generator supplies input data to a device-under-test. The result comparator compares output data of the device-under-test with expected value data and outputs a test result signal. The control circuit controls the pattern generator and the result comparator. The device-under-test and the result comparator are commonly connected to a first clock line. The pattern generator and the control circuit are commonly connected to a second clock line different from the first clock line.