BIST Leakage Detection Circuit for IC I/O Soft Failures
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Solution Overview
Problem
Integrated circuit (IC) devices are vulnerable to plasma-induced damage (PID) and electrostatic discharge (ESD) during fabrication, leading to both hard and soft failures, with existing BIST circuits unable to effectively detect small leakage currents associated with soft failures.
Innovation Solution
A BIST circuit with a serial circuit comprising transistors and a resistor, configured to detect leakage currents by controlling a switch to generate a reference current, and a detection assist circuit to quickly change voltage levels, enabling detection of sub-microampere leakage currents and reducing process-voltage-temperature variations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If existing BIST circuits are used, then hard failures can be detected, but soft failures with small leakage currents cannot be effectively detected
Solution Approach 1:
The patent changes the electrical parameters of the BIST circuit by introducing a high-impedance current source and adjustable gain amplifier, enabling the circuit to detect sub-microampere leakage currents that indicate soft failures, thereby improving measurement precision without compromising reliability
Solution Approach 2:
The patent introduces an intermediary high-impedance current source between the test node and detection circuitry, which acts as a mediator to amplify small leakage currents while blocking larger normal operating currents, enabling effective soft failure detection
2Measurement precision
If BIST circuit is made more sensitive to detect sub-microampere leakage currents, then soft failure detection improves, but the circuit becomes more complex
Solution Approach 1:
The patent segments the BIST circuit into distinct functional blocks: a high-impedance current source stage, an adjustable gain amplifier stage, and a detection logic stage. This segmentation allows each block to be optimized independently for sensitivity while maintaining overall circuit manageability and reducing effective complexity
Solution Approach 2:
The patent implements self-service through automatic gain control and calibration mechanisms within the BIST circuit, where the circuit automatically adjusts its sensitivity parameters and compensates for variations, reducing the need for external calibration and simplifying the overall system complexity
3Area of stationary object
If BIST circuit is embedded in advanced packages, then space efficiency improves, but process-voltage-temperature variations affect performance
Solution Approach 1:
The patent incorporates feedback mechanisms where the BIST circuit continuously monitors its own operating conditions and adjusts its parameters to compensate for PVT variations. This feedback loop maintains stable detection thresholds and sensitivity across process, voltage, and temperature changes, ensuring reliable operation when embedded in advanced packages
Solution Approach 2:
The patent implements dynamic adaptation by making the BIST circuit parameters adjustable and responsive to changing operating conditions. The circuit dynamically adjusts gain, threshold voltages, and timing parameters to maintain optimal performance across varying PVT conditions, transforming a static circuit into a dynamically adaptive system
Data Source
AI summary
A built-in self-test (BIST) circuit includes a first switch, a first resistor, at least one first transistor, and a control circuit. The first switch, the first resistor and the at least one first transistor are coupled in series between a first power supply terminal of a first power supply voltage and an input/output (I/O) terminal of an I/O circuit. The control circuit is configured to, in a first BIST operation, close the first switch and, while the first switch is being closed, detect a first leakage current between the I/O terminal and a second power supply terminal of a second power supply voltage different from the first power supply voltage.