A serial resistor-transistor BIST detects sub-microamp leakage at IC I/O terminals, exposing soft PID and ESD failures with stable sensitivity.
By sweeping voltage to the failure boundary and recording oscillator signals, this case enables non-destructive chip reliability measurement.
Stacked PMUs address chip-space limits in BMS IC testing while combining precise voltage and current measurement with lower-noise operation.
Stacked PMUs extend BMS test voltage coverage while reducing circuit footprint and power demands for large battery-pack conditions.
A hard clipper model generates ideal output signals to benchmark non-linear device performance.
A thermal runaway monitor calculates the ratio of stand-by current and temperature changes to detect onset conditions early.
Iterative self-testing at stepped voltage levels identifies operating outliers in single-supply integrated circuits without external equipment.
A semiconductor testing apparatus uses a switching circuit to share test pads among multiple units.
Built-in comparators measure voltage drops across power grid points to eliminate inaccurate worst-case estimates from external test files.
A detection control circuit segments register units to identify leakage current in integrated circuits.
Switch circuits dynamically control power states to reduce off-state leakage current in semiconductor devices.
A universal leakage monitoring system measures gate dielectric, sub-threshold, and junction leakages in CMOS devices using a single integrated circuit.
A scan circuit uses a configurable defect to inject detectable current for automated test equipment verification.
A test circuit varies supply voltage during scan testing to detect manufacturing defects in integrated circuits.
A testing apparatus measures static power-supply current to judge device defects.
Dynamic voltage detection identifies weak parts during production, improving defect coverage beyond standard 80% core voltage limits.
A test system determines the lowest operating voltage for integrated circuits using internal and external controllers.
Level shifters maintain signal integrity across powered-down boundaries, enabling quiescent current testing in sleep states.
A failure-prediction circuit replicates a functional circuit to detect impending component degradation through accelerated aging mechanisms.
A selectable threshold reset circuit adjusts its voltage divider ladder to enable low voltage testing of integrated circuits.
A pin electronic driver circuit forces constant voltage at the input pin of a device under test.
Source-follower amplifier isolates weak signals to reduce leakage and clock feed-through during voltage sub-sampling.