Scan Circuitry IDDQ Verification via Configurable Defect
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Solution Overview
Problem
Existing integrated circuits face challenges in accurately verifying quiescent current (IDDQ) during scan testing, as current measurement instruments may not operate correctly, leading to potential undetected manufacturing defects and incorrect configuration of automated test equipment (ATE).
Innovation Solution
The integration of verification vectors and circuitry that consume additional detectable current during configuration, allowing automated test equipment to verify the correct functioning of IDDQ test setups and detect failures by observing changes in current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If quiescent current measurement is performed during scan testing, then manufacturing defects can be detected, but the correctness of measurement instruments and ATE configuration cannot be verified
Solution Approach 1:
The patent introduces an intermediary verification circuit that includes a verification vector generator and a current consumption indicator. This intermediary component acts as a mediator between the test equipment and the device under test, providing a known reference current consumption pattern that allows verification of the measurement system's correctness without requiring external calibration equipment.
Solution Approach 2:
The verification circuit is self-contained within the device under test, using internal resources (scan chain, logic circuits) to generate verification vectors and measure current consumption. The system verifies its own measurement capability without requiring external verification equipment, making the testing process self-sufficient.
2Reliability
If additional verification circuitry is added to the scan chain, then ATE configuration can be verified, but device complexity increases
Solution Approach 1:
The verification circuit shares the scan chain infrastructure with the functional test logic, using the same scan input, scan chain elements, and output mechanisms. The verification vector generator reuses existing logic circuits and multiplexers, allowing the same hardware structure to serve both functional testing and verification purposes simultaneously.
Solution Approach 2:
The patent merges the verification functionality with the existing scan test infrastructure by integrating the verification vector generator into the scan chain and using shared logic circuits. This consolidation eliminates the need for separate verification hardware, reducing overall device complexity while maintaining verification capability.
3Measurement precision
If verification vectors are shifted into the scan chain, then current consumption changes can be detected, but test time increases
Solution Approach 1:
The verification process is implemented as a periodic operation that occurs at specific intervals during the test sequence. Verification vectors are injected at designated points in the scan chain, and current measurements are taken at corresponding time points, creating a rhythmic verification pattern that minimizes disruption to the overall test flow.
Solution Approach 2:
The verification vectors are designed to be shifted into the scan chain in advance of the actual quiescent current measurement phase. By pre-positioning the verification vectors in the scan chain elements before the measurement occurs, the system prepares the verification state beforehand, allowing for faster execution during the actual measurement window.
Data Source
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AI summary
An integrated circuitry includes a first logic block coupled between a first power supply terminal and a second power supply terminal. The first logic block includes a first scan chain and a configurable defect coupled to a scan output node of the first scan chain. The configurable defect has a logic node and a conductive element coupled between the logic node and the first or the second power supply terminal. The configurable defect is configured to, during a quiescent current testing mode, place a predetermined logic state on the logic node such that a current flows through the conductive element. The current can be detected by external equipment.