IC Testing With Power Collapsed Using Level Shifter Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional testing methods cannot perform quiescent current testing and automatic test pattern generation on integrated circuits while they are in a sleep or power-collapsed state, limiting the detection of manufacturing defects and affecting the reliability and battery life of mobile devices.
Innovation Solution
The integration of a level shifter and a power management circuit in the integrated circuit, which allows for the isolation of a collapsible power domain and the performance of IDDQ testing using a Joint Test Action Group-compatible controller, enabling the detection of defects that are undetectable with conventional techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional testing methods are used on integrated circuits in a powered-up state, then the testing can be performed with existing equipment, but manufacturing defects that are only detectable in sleep state cannot be found
Solution Approach 1:
The integrated circuit is divided into separate power domains - a main power domain that remains powered and a collapsible power domain that can be powered down. This segmentation enables independent control of power states, allowing testing to occur in the main power domain while the collapsible power domain is in sleep state, thus detecting defects that only manifest when powered down.
Solution Approach 2:
A level shifter is introduced as an intermediary component between the main power domain and the collapsible power domain. The level shifter maintains signal level compatibility across power domain boundaries, enabling testing signals to pass through while the collapsible power domain is powered down. This intermediary allows the testing equipment to interface with the circuit in different power states without direct power coupling.
2Reliability
If power is collapsed to a power domain for sleep state testing, then defects in sleep state can be detected, but signal level differences between powered and unpowered domains create testing challenges
Solution Approach 1:
The level shifter serves as a mediator that handles signal level translation between the main power domain and the collapsible power domain. When the collapsible power domain is powered down, the level shifter maintains proper signal levels for testing without requiring complex isolation circuitry, thus detecting sleep state defects while managing complexity through a dedicated level translation component.
Solution Approach 2:
The collapsible power domain is designed with local power control, allowing only specific portions of the circuit to be powered down while the main power domain remains active. This local quality approach enables sleep state testing in specific regions without affecting the entire circuit, reducing the complexity of full-system power management during testing.
3Productivity
If conventional ATPG techniques are used, then standard testing can be performed, but testing cannot be performed when the IC is in sleep or power-collapsed state
Solution Approach 1:
The testing system is designed with multi-functionality to operate in multiple power states. The main power domain can support both powered-up testing and powered-down testing of the collapsible domain, making the testing system universal across different operational states. This enables ATPG techniques to be applied regardless of the power state of specific circuit portions, significantly expanding testing coverage.
Solution Approach 2:
By segmenting the circuit into main and collapsible power domains, the system enables testing to proceed in the main power domain while the collapsible domain is powered down. This segmentation allows ATPG testing to be performed across different power states, increasing productivity by eliminating the requirement for the entire circuit to be powered during testing.
Data Source
AI summary
Provided are apparatus and methods for testing an integrated circuit. In an exemplary method for testing an integrated circuit, a test controller and a power manager are integrated into a main power domain of the integrated circuit. The test controller can be Joint Test Action Group-compatible. An isolation signal is generated using the power manager. The isolation signal can comprise at least one of a freeze signal configured to isolate an input-output port of the integrated circuit, and a clamp signal configured to isolate a functional module of the integrated circuit. The isolation signal can be stored in a boundary scan register controlled with the test controller. The main power domain is isolated from a power-collapsible domain of the integrated circuit with the isolation signal. Power of the power-collapsible domain is collapsed. When power is collapsed, the power-collapsible domain is tested using the test controller and the power manager. The testing of the power-collapsible domain can comprise testing a power supply current. When power to the power-collapsible domain is collapsed, a level shifter output can be held constant to an output level based on a pre-collapse input from the power-collapsible domain.