Semiconductor Testing Apparatus With Switching Circuit For Pad Sharing

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Solution Overview

Problem

The semiconductor industry faces challenges in efficiently testing semiconductor devices due to limited space on wafers, which restricts the number of test units and pads, leading to inadequate testing capabilities and noise interference from parasitic leakage.

Innovation Solution

A testing apparatus is developed that uses a control circuit and switching circuit to selectively activate testing units, allowing a low number of testing pads to be shared among multiple units, and employs a multi-dimensional sweeping process to minimize leakage current, thereby improving signal-to-noise ratio.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the number of test pads is increased to support more test units, then the testing capability is improved, but the chip area consumption increases

Engineering Contradiction:
Improvetesting capabilityVSAvoidchip area
Core Design Contradiction:
Adaptability or versatilityVSArea of stationary object

Solution Approach 1:

The patent implements a switching circuit that allows a small number of test pads to be dynamically shared among multiple test units. The switching circuit routes test signals from limited test pads to different test units based on control signals, enabling one test pad to serve multiple test units sequentially. This multi-functional approach resolves the contradiction by maintaining high testing capability while minimizing the number of physical test pads required on the chip.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Productivity

If more test units are implemented to improve testing efficiency, then the productivity is improved, but the device complexity increases

Engineering Contradiction:
Improvetesting efficiencyVSAvoidnumber of test units
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent introduces a switching circuit as an intermediary between the test pads and test units. This switching circuit manages the complex connections between multiple test units and limited test pads, simplifying the overall system architecture. The switching circuit receives control signals and dynamically connects appropriate test units to test pads, enabling efficient testing of multiple units without requiring proportional increases in test pad infrastructure.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Area of stationary object

If traditional testing methods are used with limited test pads, then the chip area is conserved, but the measurement precision deteriorates due to parasitic leakage

Engineering Contradiction:
Improvechip areaVSAvoidtest measurement accuracy
Core Design Contradiction:
Area of stationary objectVSMeasurement precision

Solution Approach 1:

The patent extracts and compensates for parasitic leakage effects by implementing a forcing-sensing scheme. Separate forcing pads apply test signals while dedicated sensing pads measure the actual signals received by test units. This separation allows the system to distinguish between genuine test unit responses and parasitic leakage currents, thereby maintaining measurement precision even with minimal test pads on the chip.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS11150296B2Method and apparatus for testing a semiconductor device
Publication Date: 2021.10.19 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11150296B2 patent drawing
  • US11150296B2 patent drawing
  • US11150296B2 patent drawing

AI summary

The present disclosure provides methods for testing and evaluating electrical parameters of electronic circuits. An exemplary method includes providing a device-under-test electrically coupled to a testing apparatus; and determining an optimum value of a first electrical parameter and an optimum value of a second parameter by testing the device-under-test according to a set of first electrical parameter values and a set of second electrical parameter values. The optimum value of the first electrical parameter and the optimum value of the second parameter are determined based on an electrical noise response of the device-under-test.