Test Circuit for Low Voltage Scan Testing of Integrated Circuits
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Solution Overview
Problem
Current very low voltage (VLV) scan testing methods for integrated circuit devices are inefficient due to extended test times, which increase costs and do not effectively detect manufacturing defects like interconnect bridging and gate-oxide shorts at normal voltage levels.
Innovation Solution
The method involves varying the operating voltage and clock frequency during scan testing, applying normal voltage and clock frequency during the scan shift phase and reducing them during the scan capture phase to detect faults efficiently, allowing for faster test completion while maintaining high test quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If very low voltage scan testing is performed to detect manufacturing defects, then defect detection capability is improved, but test time increases significantly
Solution Approach 1:
The test cycle is segmented into distinct phases: scan shift phase at normal voltage for fast testing, and scan capture phase at reduced voltage for defect detection. This segmentation allows each phase to operate under optimal conditions, resolving the contradiction between speed and detection capability.
Solution Approach 2:
The voltage level is dynamically adjusted based on the test phase requirements. The system transitions between normal voltage during scan shift operations and reduced voltage during scan capture operations, enabling both fast testing and effective defect detection without compromising either aspect.
2Measurement precision
If constant reduced voltage is maintained throughout scanning and capture phases, then defect detection is improved, but test speed decreases
Solution Approach 1:
The test cycle is divided into scan shift phase and scan capture phase, allowing different voltage levels to be applied to different phases. This segmentation enables fast scanning at normal voltage while maintaining reduced voltage only during the critical capture phase for defect detection.
Solution Approach 2:
Instead of maintaining reduced voltage throughout the entire test cycle, the system applies reduced voltage only partially during the scan capture phase when defect detection is most critical. This partial application of low voltage maintains detection capability while avoiding the penalty of slowed scanning operations.
3Productivity
If scan testing is performed at normal voltage level, then test speed is maintained, but manufacturing defects remain undetected
Solution Approach 1:
The test cycle is segmented into scan shift phase at normal voltage for high-speed operation and scan capture phase at reduced voltage for enhanced defect detection. This segmentation ensures that both speed and detection capability are achieved in their respective phases.
Solution Approach 2:
The voltage parameter is changed between different phases of the test cycle. Normal voltage is used during scan shift to maintain speed, while reduced voltage is applied during scan capture to improve defect detection, thus resolving the contradiction between speed and detection precision.
Data Source
AI summary
Test circuitry for an integrated circuit (IC) that has a scan chain includes a control unit for applying a test pattern and a clock signal to the scan chain, and for varying the level of a supply voltage during a scan test procedure. In a first test phase, the supply voltage is set to the rated voltage level of the IC while a test pattern is shifted into the scan chain at a fast rate. A second, capture phase is run at a lower rate and the supply voltage is reduced to a lower level such that defects that cannot be detected when the capture phase is run at the rated voltage are observable yet switching elements in the IC still function correctly. Running the shift phase at the higher speed reduces the overall test time compared with known very low voltage (VLV) scan test procedures.