Leakage Detection Control Circuit for IC Standby Mode
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Solution Overview
Problem
Existing detection methods for leakage current in integrated circuits due to process flaws are inefficient and economically unfeasible, especially during the standby mode, where the vast number of register combinations make defect detection extremely difficult.
Innovation Solution
A detection control circuit comprising a register unit with a clock signal input, reset signal input, and a logic gate that generates a fixed output signal to detect leakage current, effectively controlling the logic gate with a control signal to maintain a fixed state and identify leakage issues in integrated circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all register combinations are tested in standby mode to detect leakage current, then detection completeness is improved, but device complexity and testing cost increase exponentially
Solution Approach 1:
The patent divides the circuit into functional blocks (registers, combinational logics, memory units) and assigns control signals to each block. Instead of testing all possible register combinations, the control circuit segments the testing into manageable parts by independently controlling each functional block's state, thereby reducing the exponential complexity while maintaining detection coverage.
Solution Approach 2:
The control circuit pre-configures the circuit into specific test patterns before actual leakage detection. By preliminarily setting registers and combinational logics to predetermined states through control signals, the system avoids the need to exhaustively test all possible combinations during operation, significantly reducing testing complexity while ensuring critical leakage paths are covered.
2Measurement precision
If traditional detection methods are used for high register counts, then detection accuracy is maintained, but testing time and resource consumption become prohibitively high
Solution Approach 1:
The control circuit implements periodic testing cycles where the circuit is switched between operational mode and test mode. During test mode, predetermined patterns are applied and leakage is detected. This periodic approach allows the system to maintain high detection accuracy for critical paths while avoiding continuous exhaustive testing of all register combinations, thereby reducing overall testing time.
3Reliability
If exhaustive testing of all register combinations is performed, then all leakage defects are detected, but the cost becomes economically unfeasible for modern integrated circuits
Solution Approach 1:
The control circuit applies partial testing by focusing on critical paths and high-risk areas where leakage is most likely to occur. Instead of exhaustively testing all register combinations, the system applies test patterns to strategically selected functional blocks and register groups. This partial action approach maintains adequate defect detection coverage while dramatically reducing testing cost and complexity for production environments.
Data Source
AI summary
The present invention discloses a detection control circuit for preventing a leakage current, which comprises a register unit comprising a clock signal input terminal for receiving a clock signal; a reset signal input terminal, for receiving a reset signal; a signal generating terminal, for generating a logic signal; and a logic gate, coupled to said register unit, comprising a first signal input terminal for receiving said logic signal; a second signal input terminal for receiving a control signal; and a signal output terminal, for outputting an output signal according to said logic signal and said control signal; wherein said control signal controls said logic gate so as to keep said output signal to be in a fixed state which detects a leakage current in an integrated circuit due to the process flaw.