VLV Test Voltage Determination Circuit for IC Defect Detection
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current very low voltage (VLV) testing of integrated circuits is limited as it often requires operating voltages set at 80% of the core voltage, which may not be sufficient to identify all defectivity, especially as defectivity expectations decrease to levels below 1 parts per million, with some ICs unable to operate at lower voltages.
Innovation Solution
A testing circuit in combination with level shifters and a supply voltage detection circuit determines the minimum supply voltage at which both logic and level shifters can operate, allowing for VLV testing at voltages lower than 80% of the core voltage by ramping up the supply voltage and recording the level at which the ring oscillator becomes operational.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the operating voltage is set to 80% of the core voltage for VLV testing, then the testing can be performed on most ICs, but the defectivity identification capability is insufficient for achieving less than 1 PPM defectivity levels
Solution Approach 1:
The patent implements a dynamic voltage determination approach where the test voltage is not fixed at 80% of core voltage, but is instead dynamically determined for each IC device by measuring its actual minimum operating voltage through a ring oscillator-based detection circuit. This allows the testing system to adapt the voltage level to each device's characteristics, enabling lower voltage testing for devices that can tolerate it while maintaining compatibility with devices that require higher voltages.
Solution Approach 2:
The patent changes the test voltage parameter from a fixed value (80% of core voltage) to a variable value determined by actual device characteristics. By using a detection circuit that measures the minimum operating voltage of each IC and setting the test voltage based on this measurement, the system achieves lower test voltages for compatible devices, thereby improving defectivity identification capability while maintaining adaptability across different IC types.
2Reliability
If the operating voltage is reduced to enable identification of more defectivity, then defect coverage improves, but some ICs are unable to operate and be tested
Solution Approach 1:
The patent performs a preliminary voltage determination action before actual VLV testing. A detection circuit using a ring oscillator measures the minimum operating voltage of each IC device in advance. Based on this preliminary measurement, the system sets an appropriate test voltage that is low enough to reveal defects but high enough to ensure the IC can operate during testing. This preliminary characterization eliminates the need to choose between low voltage and operability.
Solution Approach 2:
The patent introduces an intermediary detection circuit that includes a ring oscillator, voltage detector, and control logic. This intermediary system acts as a mediator between the test voltage source and the IC under test, first characterizing the IC's voltage requirements and then setting an appropriate test voltage. This intermediary layer enables the system to achieve low test voltages for defect detection while ensuring each IC operates within its safe voltage range.
Data Source
AI summary
An integrated circuit device includes general purpose input/output (I/O) circuitry having a transmit level shifter circuit in a transmit I/O circuit and a receive level shifter circuit in a receive I/O circuit. The integrated circuit device also includes an I/O pad which couples an output of the transmit level shifter circuit to an input of the receive level shifter circuit, a counter circuit, an inverter circuit coupled between the receive level shifter circuit and the counter circuit, and a logic gate. The logic gate includes a first input coupled to an output of the inverter circuit, a second input coupled to a counter_done signal from the counter circuit, and an output coupled to provide a data_out signal to an input of the transmit level shifter circuit.