On-Chip BIST for High-Speed Memory Data Path Testing
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Solution Overview
Problem
High-speed data paths in semiconductor memory devices are prone to errors due to increased operational speeds, making it challenging to maintain data integrity, especially when testing individual dies externally, which is costly and time-consuming, and can lead to discarding entire multi-die packages if a single die is defective.
Innovation Solution
Implementing on-chip test techniques for high-speed IO data path testing using built-in self-test (BIST) methods that generate, transfer, and compare data test patterns, allowing for high-speed data path testing without external testers, thereby reducing costs and improving yield by identifying defective dies early in the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If external testers are used to test high-speed data paths, then data integrity can be verified, but test costs increase and test time increases
Solution Approach 1:
The patent implements built-in self-test (BIST) functionality where the memory device tests its own high-speed data paths using internal test circuits and test patterns, eliminating the need for external testers. This self-service approach reduces test costs and time while maintaining data integrity verification through internal comparison circuits that validate data during manufacturing testing.
2Reliability
If external testers are used for individual die testing, then data path errors can be detected, but entire multi-die packages may be discarded
Solution Approach 1:
The patent implements partial testing by focusing BIST resources on testing only the high-speed data path circuits that are critical for operation, rather than performing exhaustive testing on entire multi-die packages. This selective approach detects errors in specific data paths while preserving functional dies, thereby maintaining manufacturing yield while ensuring reliability of the high-speed interface.
3Speed
If high-speed data transfer is implemented, then operational performance improves, but data errors increase along the data path
Solution Approach 1:
The patent incorporates feedback mechanisms through built-in comparison circuits that continuously monitor data integrity during high-speed transfers. Test patterns are transmitted through the high-speed data path and compared against expected values, providing immediate feedback on data integrity. This feedback loop enables detection and correction of errors that occur during high-speed operation, maintaining both speed and reliability.
Data Source
AI summary
Techniques are presented for testing the high-speed data path between the IO pads and the read/write buffer of a memory circuit without the use of an external test device. In an on-chip process, a data test pattern is transferred at a high data rate between the read/write register and a source for the test pattern, such as register for this purpose or the read/write buffer of another plane. The test data after the high-speed transfer is then checked against its expected, uncorrupted value, such as by transferring it back at a lower speed for comparison or by transferring the test data a second time, but at a lower rate, and comparing the high transfer rate copy with the lower transfer rate copy at the receiving end of the transfers.