Digital Storage TRIZ Cases

On-chip built-in self-test circuits transfer and compare data patterns to verify integrity without external testers.

A memory power management method switches DIMMs between low and high power states to reduce consumption.

A pre-signal generator creates pre-latch pulse signals to synchronize data output control in semiconductor devices.

Segmented sense amplifier stages reduce signal propagation time by compensating for metal resistance in long SRAM data lines.

Segmenting neural network parameters into critical and non-critical bits allows storing them in separate ECC and non-ECC memories to reduce overhead.

A transceiver circuit uses a transfer buffer to write and read back data simultaneously.

Adjusting pull-down and pass gate dimensions enhances write trip voltage to meet 6σ yield criteria at the 22 nm scale.

A semiconductor pad data alignment circuit merges conversion and driving functions to transmit parallel data through global lines.

A semiconductor memory device adjusts write-in and read-out pulse widths to maintain reliable data transmission across varying operation frequencies.

Delay adjustment circuits synchronize the internal clock with read data strobe signals, eliminating FIFO buffers and reducing DDR DRAM read latency.

A bridge device converts global control signals into local formats to operate discrete memory chips within a composite module.

A wordline voltage generator supplies dynamic negative voltages to memory cell wordlines.

Two-phase error detection latches read data to identify intermittent failures caused by charge leakage, preventing data loss in high-density memory devices.

A memory cell configuration using semiconductor elements enables controlled voltage applications during write and erase operations.

A charge transfer device moves electrical signals between digit lines and sense components to enable precise logic state detection.

A semiconductor memory cell uses a shared connection layer to link variable resistance elements for efficient data storage.

Opposite easy-axis biasing in stacked toggle memory cells reduces switching fields and power consumption while resolving half-select issues.

A magnetoresistive memory cell monitors electrical potential during write operations to terminate current supply upon data completion.

A DRAM chip uses a temperature sensor to adjust its refresh period based on flash memory heat levels.

Segmenting bit line precharging eliminates unnecessary write line charging, reducing SRAM leakage current by 50% and lowering active power consumption.

Dual precharge circuits apply distinct voltages to bit lines and complementary bit lines during FRAM test mode.

Pull-down transistors actively pull down adjacent word line voltages to prevent unintended discharge caused by capacitive coupling interference.

A bit-cell voltage distribution circuit connects operating voltage before word line signals arrive at the memory cell.

Dynamic bitline precharging resolves the trade-off between half-column stability during writes and read current by adjusting voltage potentials per operation.

I/O circuit blocks data strobe signals during unselected periods, reducing power consumption while maintaining transfer capability.

A memory module breaks instructions into elementary operations for internal execution.

Parallel voltage paths in a phase-change memory device enable direct cell access, resolving complexity issues from separate addressing routes.

A memory system segments address lines to specify individual banks for precharge operations.

A termination control circuit generates a period signal to activate termination resistors during write operations.

A neuromorphic device design shares a single logic element across multiple synapse blocks to simplify circuitry and reduce chip size.

A semiconductor device generates serial, clock, and random data patterns using a single processing circuit for memory testing.

Dynamic voltage regulation protects SRAM cells from hot-carrier-injection damage during programming operations.

Pre-biasing the reference bit line compensates for offset noise caused by semiconductor variations, improving sensing margin.

A memory interface circuit supports both synchronous and asynchronous modes using configurable address, data, and control logic.

A power-on-reset circuit deactivates predecoded address lines upon startup to prevent premature word line activation.

An interface unit routes prioritized input data through parallel processors and an access management unit, reducing jitter in hard real-time systems.

A semiconductor integrated circuit input output circuit routes data to enabled memory banks via a repeater and control unit.

Integrating level shifters into input receivers and output drivers reduces semiconductor area while minimizing access time delays.

Separate precharge logic driven by a second power supply aligns timing with array access operations, reducing drive fight current and improving stability.

A semiconductor memory device isolates local data lines to reduce sense amplifier load.

Segmented memory arrays paired with dedicated peripheral circuits enable targeted read and write operations for distinct data characteristics.

Dynamic drain bias adjustment reduces second bit interference and read disturb errors while widening the threshold voltage window for accurate data retrieval.

Merging error checking and correction circuits into a single shared unit reduces occupied area while maintaining data retention reliability.

Multi-layer bit lines reduce SRAM cell resistance using composite interconnect structures, improving operational speed and writing characteristics.

A pull-down transistor in word line drivers provides a controlled discharging path to stabilize voltage levels across memory cells.

Dual sense amplifiers on a segmented global data bus reduce signal transmission distance and double bandwidth without adding tracks.

Segmenting the SRAM into separate voltage domains with a level shifter minimizes read errors caused by lag between word line disable and sense amplifier enable.