Sense Amplifier Offset Cancellation for DRAM Sensing Margin
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Dynamic random access memory (DRAM) performance is compromised due to offset noise caused by variations in semiconductor elements, leading to reduced effective sensing margin and voltage difference between bit lines.
Innovation Solution
A sense amplifying circuit that performs offset cancellation operations by pre-biasing the voltage level of a reference bit line based on the data value of the bit line, using a sequence of precharge, offset cancellation, charge sharing, and amplification operations, with specific switches and transistors configured to enhance voltage difference and sensing margin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If offset cancellation operation is performed to compensate for PVT variations, then sensing margin is improved, but device complexity increases due to additional switches and control circuits
Solution Approach 1:
The patent performs offset cancellation operation before the main sensing operation by pre-biasing the reference bit line to match the voltage level of the active bit line. This preliminary action compensates for PVT variations in advance, improving sensing margin without requiring complex real-time adjustments during the critical sensing phase.
Solution Approach 2:
The patent introduces a reference bit line as an intermediary element that mirrors the voltage characteristics of the active bit line. By coupling the reference bit line to the same memory cell during offset cancellation, it serves as a mediator to transfer and match voltage levels, enabling offset compensation without directly modifying the main sensing circuitry.
2Measurement precision
If pre-biasing of reference bit line is performed to maximize voltage difference, then sensing accuracy is improved, but operation time increases due to additional operation stages
Solution Approach 1:
The patent implements sensing operations in distinct periodic stages: precharge phase, offset cancellation phase, and main sensing phase. Each stage performs a specific function with optimized timing, allowing the circuit to methodically prepare and execute the sensing task efficiently rather than continuously adjusting parameters.
Solution Approach 2:
The reference bit line is pre-biased to the appropriate voltage level during the precharge and offset cancellation phases before the main sensing operation begins. This preliminary preparation ensures that when the actual sensing occurs, the voltage difference is already maximized, eliminating the need for time-consuming adjustments during the critical sensing window.
3Manufacturing precision
If multiple switches are used for offset cancellation and pre-biasing, then voltage control precision is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies different switch configurations to different parts of the circuit based on their specific functional requirements. For example, offset cancellation switches connect the reference bit line to ground or VBLP, while pre-biasing switches connect it to the active bit line. Each switch is optimally positioned and sized for its local function, achieving precise voltage control without requiring all switches to be identical or overly complex.
Data Source
AI summary
According to an embodiment of the present disclosure, a semiconductor memory device includes a bit line sense amplifier coupled between a pull-up voltage line and a pull-down voltage line, and suitable for sensing a voltage difference between first and second bit lines by sequentially performing a precharge operation, an offset cancellation operation, a charge sharing operation, and an amplification operation, wherein the bit line sense amplifier pre-biases a voltage level of the second bit line depending on a voltage level of the first bit line during the charge sharing operation; and a driving circuit suitable for supplying operating voltages to the pull-up voltage line and the pull-down voltage line during the offset cancellation operation, the charge sharing operation, and the amplification operation.