Dual Rail Memory Level Shifters for Area and Delay Trade-offs
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Dual rail power supply systems for memory devices face challenges such as large area overhead, significant performance impact, yield issues, and poor performance due to bit-cell stability problems caused by uncorrelated VDD and VDDA power supplies, especially when the periphery voltage is greater than the array voltage.
Innovation Solution
Implementing a dual rail memory architecture where the core and periphery circuits operate at different voltages, with level shifters integrated into input receivers and output drivers rather than deeper in the memory, allowing for uncorrelated power supply voltages and reducing the number of level shifters required, thus simplifying the layout and reducing area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If level shifters are integrated into input receivers and output drivers, then area overhead is reduced, but performance impact increases due to delays in access time
Solution Approach 1:
The patent applies preliminary action by pre-charging and pre-discharging the level shifter nodes before actual data transfer occurs. The level shifters are designed with precharge circuits that prepare the voltage levels in advance, reducing the propagation delay during actual data access operations while maintaining the area-efficient integration in input receivers and output drivers.
2Loss of energy
If uncorrelated power supply voltages are used for periphery and array, then leakage power is reduced, but bit-cell stability deteriorates when periphery voltage exceeds array voltage
Solution Approach 1:
The patent introduces an intermediary mechanism in the form of controlled level shifters that mediate between the uncorrelated periphery voltage domain and array voltage domain. These level shifters include control logic that prevents direct exposure of bit-cells to voltage differences that would compromise stability, while still allowing the periphery to operate at higher voltages for reduced leakage power.
Solution Approach 2:
The patent dynamically adjusts operating parameters of the bit-cells based on the voltage relationship between periphery and array domains. When periphery voltage exceeds array voltage, the system modifies bias conditions and timing parameters to maintain bit-cell stability, enabling the system to exploit uncorrelated power supplies for leakage reduction without sacrificing reliability.
3Loss of energy
If dual rail power supply is implemented, then leakage power is reduced, but device complexity increases due to multiple power domains
Solution Approach 1:
The patent merges the dual rail power supply implementation with the existing input receiver and output driver structures. By integrating level shifters directly into these standard interface components rather than adding separate power management circuits, the patent reduces the overall device complexity while still achieving leakage power reduction through uncorrelated power supplies.
Data Source
AI summary
A dual rail memory operable at a first voltage and a second voltage includes an input circuit, an output circuit and a clock generator circuit coupled with the input circuit. The input circuit is operable to receive at least a first input signal referenced to the first voltage and to generate a second input signal referenced to the second voltage. The output circuit is operable to receive at least a first output signal referenced to the second voltage and to generate a second output signal referenced to the first voltage. The clock generator circuit is operable to receive a first clock signal referenced to the first voltage and to generate a second clock signal referenced to the second voltage, a logic state of the second clock signal being a function of a logic state of the first clock signal.