SRAM Read Bit Line Precharge Control for Leakage Reduction
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Solution Overview
Problem
Conventional SRAM designs experience significant leakage current and power consumption due to precharging of both read and write bit lines, even when only one SRAM bank is accessed, leading to excessive power usage and reduced efficiency.
Innovation Solution
Implementing a precharge transistor that is only activated during read operations and keeping write bit lines unprecharged, with the read bit line being precharged either before or in parallel with the evaluation phase, while write bit lines are not precharged, thereby reducing leakage and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If precharge transistors are activated for both read and write bit lines in conventional SRAM designs, then memory performance is maximized through proper bit line preparation, but leakage current increases significantly consuming excessive power
Solution Approach 1:
The patent divides the bit line precharging function into separate read bit line precharge and write bit line precharge operations. Only the read bit line is precharged before read operations, while write bit lines are not precharged. This segmentation eliminates unnecessary precharging of write bit lines, reducing leakage current by 50% or more while maintaining read operation performance.
Solution Approach 2:
The precharge transistor for the read bit line is activated only during the decode time period when a read operation is to be performed, and deactivated during other periods. This periodic activation ensures the bit line is precharged only when needed, minimizing continuous leakage current while maintaining proper precharge timing for read operations.
2Reliability
If address transistors are increased in size to improve read performance, then read capability is enhanced, but leakage current through deactivated address transistors increases significantly
Solution Approach 1:
The read bit line is precharged to a high logic level before the read operation begins, during the decode time period. This preliminary precharging ensures that when the address transistor is activated, the bit line is already in the correct state, allowing for proper read operation without requiring excessive transistor sizing that would increase leakage.
3Reliability
If write bit lines are precharged along with read bit lines, then all bit lines are properly prepared for their respective operations, but unnecessary power is consumed precharging write bit lines that are not accessed
Solution Approach 1:
The patent extracts the precharging function specifically for read bit lines only, removing the precharging operation from write bit lines. Write bit lines are prepared through other means (such as being held at a default level or charged through write drivers only when needed), eliminating the unnecessary precharge transistor leakage associated with write bit lines while maintaining proper read operation functionality.
Data Source
AI summary
Integrated circuits with volatile random-access memory cells are provided. A memory cell may be coupled to write bit lines and a read bit line. The write bit line may not be coupled to any precharge circuitry. The read bit line may only be precharged during memory access operations. In one suitable arrangement, the read bit line may be precharge immediately after an address decoding operation and before an evaluation phase. In another suitable arrangement, the read bit line may be precharged after an addressing decoding operation and in parallel with the evaluation phase. In either arrangement, a substantial amount of leakage and active power can be reduced.