Memory Interface Clock Delay for Read Latency Reduction

Solution Overview

Problem

Conventional memory interface circuits require a FIFO for synchronization between the internal clock and read data strobe, leading to read latency in DDR DRAM devices due to phase misalignment and power-saving issues.

Innovation Solution

A memory interface circuit with a delay adjustment circuit to synchronize the internal clock with the read data strobe by delaying the clock and control signals, allowing direct sampling of read data without the need for a FIFO, using a phase shifter to align the clock edges with the read strobe signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a FIFO is used for synchronization between internal clock and read data strobe, then phase misalignment is compensated, but read latency is introduced

Engineering Contradiction:

ImprovesynchronizationVSAvoidread latency

Core Design Contradiction:

ReliabilityVSLoss of time

Solution Approach 1:

The patent applies preliminary action by delaying the internal clock signal and control signals before they reach the memory device. This pre-adjustment of timing allows the clock edges to align with the read data strobe at the memory device, eliminating the need for FIFO-based synchronization and reducing read latency while maintaining reliable phase alignment.

Inventive Principle:

Principle #10Preliminary action

2Ease of operation

If the read data strobe is shifted 90 degrees in PHY, then data sampling is enabled, but synchronization with internal clock requires FIFO

Engineering Contradiction:

Improvedata samplingVSAvoidsynchronization circuitry

Core Design Contradiction:

Ease of operationVSDevice complexity

Solution Approach 1:

The patent applies preliminary action by delaying the internal clock signal and control signals before they reach the memory device. This pre-adjustment of timing allows the clock edges to align with the read data strobe at the memory device, eliminating the need for FIFO-based synchronization and reducing read latency while maintaining reliable phase alignment.

Inventive Principle:

Principle #10Preliminary action

3Use of energy by moving object

If IO circuits are turned on only during read/write operations, then power consumption is reduced, but timing control becomes more difficult

Engineering Contradiction:

Improvepower consumptionVSAvoidtiming control

Core Design Contradiction:

Use of energy by moving objectVSEase of operation

Solution Approach 1:

The patent applies preliminary action by delaying the internal clock signal and control signals before they reach the memory device. This pre-adjustment of timing allows the clock edges to align with the read data strobe at the memory device, eliminating the need for FIFO-based synchronization and reducing read latency while maintaining reliable phase alignment.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS9058898B1Apparatus for reducing read latency by adjusting clock and read control signals timings to a memory device

Publication Date: 2015.06.16 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present invention discloses an efficient way to read data from a memory device by aligning an internal clock of the memory interface circuit with the read data strobe signal from the memory device by delaying the internal clock along with control signals for reading the memory device before transmitting them to the memory device, wherein the internal clock of the memory controller can sample the read data from the memory device directly without using a FIFO device between the internal clock and the read data strobe so as to reduce latency of reading data from the memory device. For example, the memory device can be a double-data-rate (DDR) DRAM device, and the control signals includes command and address signals of the DDR DRAM device.