SRAM Cell Transistor Sizing for Noise Margin and Write Assist
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Static random access memory (SRAM) bit cells at the 22 nm scale fail to meet the 6σ yield criteria due to inadequate Static Noise Margin (SNM) and Write Ability Margin (WAM) parameters, necessitating improvements in noise margins and write trip voltage.
Innovation Solution
The implementation of read-preferred SRAM cell structures with two inverters, each having a pull up transistor with a feedback loop, and a write assist circuit with two outputs that couple to the bit line sources and back-gate biases of transistors, enhancing random static noise margin and word line write trip voltage without requiring additional voltage generators.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the 6T SRAM bit cell is miniaturized to 22 nm scale, then the transistor density and memory capacity increase, but the SNM and WAM parameters fail to meet 6σ yield criteria
Solution Approach 1:
The patent applies different transistor widths to different positions within the SRAM bit cell. Specifically, the pull-down transistor connected to the write bit line has a narrower width (W_PD1) compared to the other pull-down transistor (W_PD2), creating local quality variations that optimize both write ability and noise margins at the 22 nm scale
Solution Approach 2:
The patent changes the geometric parameters of the transistors, specifically the widths of the pull-down transistors, to optimize the SNM and WAM parameters. By adjusting W_PD1 and W_PD2 to different values, the design achieves improved write ability margin while maintaining adequate static noise margin at the miniaturized 22 nm node
2Reliability
If the pass gate transistor length is increased to improve RSNM, then the random static noise margin improves, but the cell space increases and I cell decreases
Solution Approach 1:
The patent increases the length of only the pass gate transistor (L_PG) while keeping other transistor dimensions optimized, creating a localized improvement in RSNM without proportionally increasing the entire cell area. This selective dimension adjustment achieves the desired noise margin improvement with minimal space overhead
3Ease of manufacture
If the pull down transistor widths are made equal to pass gate transistor widths, then the lithography layout becomes friendlier and I cell improves, but RSNM is slightly degraded
Solution Approach 1:
The patent sets W_PD1 equal to W_PG1 and W_PD2 equal to W_PG2, creating parameter symmetry that simplifies lithography manufacturing. The slight RSNM degradation from this configuration is compensated by the optimized asymmetric pull-down transistor widths and the increased pass gate length, achieving an overall balance between manufacturability and performance
4Reliability
If a write assist circuit is added to improve write ability, then the word line write trip voltage improves, but the circuit complexity increases
Solution Approach 1:
The patent integrates the write assist functionality directly into the existing 6T bit cell structure by strategically sizing the pull-down transistors and pass gates. The asymmetric pull-down transistor design (with W_PD1 < W_PD2) provides inherent write ability enhancement without requiring separate assist circuits, merging the write assist function into the basic cell structure
Solution Approach 2:
The bit cell structure itself provides write ability improvement through its asymmetric transistor configuration. The narrower W_PD1 creates a weaker pull-down effect during write operations, allowing easier bit flipping without external assist circuits. The cell serves its own write assist function through its intrinsic geometric design
Data Source
Figure 1~2
Figure 3~4
Figure 5~6
AI summary
Static random access memories (SRAM) with read-preferred cell structures and write drivers are disclosed. In one embodiment, the SRAM has a six transistor bit cell. The read-preferred bit cell is implemented by providing two inverters, each having a pull up transistor, a pull down transistor and a pass gate transistor. Each pull up transistor is associated with a feedback loop. The feedback loop improves random static noise margin. Each transistor has a width and a length. The lengths of the pass gate transistors are increased. The widths of the pull down transistors are equal to one another and also equal to the widths of the pass gate transistors. The widths of the pass gate and pull down transistors may also be increased relative to prior designs. A write assist circuit may also be used to improve performance.