SRAM Bit Line Resistance via Multi-Layer Interconnects
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Solution Overview
Problem
Current semiconductor memory devices using buried interconnects with metal materials like tungsten have higher resistance, leading to lower operational speed and deteriorated writing characteristics for SRAM cells, with increased area and parasitic capacitance limitations.
Innovation Solution
The layout configuration of SRAM cells incorporates bit lines formed in both the buried interconnect layer and the M1 line layer, reducing resistance while maintaining a compact device area by utilizing complementary bit line pairs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If bit lines are formed only in the buried interconnect layer using metal materials like tungsten, then the device area is kept compact, but the resistance is high leading to lower operational speed and deteriorated writing characteristics
Solution Approach 1:
The patent extends the bit line structure from a single layer (buried interconnect layer) to multiple layers by adding M1 line layer components. This vertical dimensionality change allows the bit line to span across different interconnect layers, reducing resistance without significantly increasing the planar device area footprint.
Solution Approach 2:
The patent employs composite interconnect structures where the bit line is formed using different materials in different layers - tungsten in the buried interconnect layer and copper in the M1 line layer. This composite approach leverages the low resistance of copper while maintaining the structural benefits of the buried interconnect architecture.
2Reliability
If the line width of the bit line in the buried interconnect layer is increased to improve the operational lower limit voltage, then the area of the SRAM cell becomes larger
Solution Approach 1:
Instead of increasing line width in the single buried interconnect layer, the patent adds vertical dimension by extending the bit line into the M1 line layer. This multi-layer approach increases the effective conductive cross-section and reduces resistance, thereby improving operational voltage characteristics without expanding the planar cell area.
Solution Approach 2:
The patent uses copper material in the M1 line layer portion of the bit line, which has lower resistance than tungsten. This material substitution in the upper layer compensates for the limited width available in the buried interconnect layer, improving voltage operation without area penalty.
3Reliability
If the length of the bit line in the depth direction is extended to reduce the resistance, then the reduction is limited due to manufacturing restriction and parasitic capacitance increases causing operation speed to decrease
Solution Approach 1:
The patent utilizes the vertical dimension by forming bit line portions in both the buried interconnect layer and the M1 line layer above it. This multi-layer configuration reduces resistance by providing parallel conduction paths without excessively increasing the depth length, thereby limiting parasitic capacitance growth while achieving resistance reduction.
Solution Approach 2:
By using copper in the M1 layer portion of the bit line, the patent achieves lower resistance with shorter effective current path length compared to using tungsten throughout. This material differentiation allows resistance reduction without proportionally increasing the bit line depth, thus controlling parasitic capacitance.
Data Source
AI summary
A 1-port SRAM cell includes: a load transistor, a load transistor, a drive transistor, a drive transistor, an access transistor having nodes, one of which is connected to a buried interconnect and a line; and an access transistor having nodes, one of which is connected to a buried interconnect and a line. The buried interconnects are formed in the buried interconnect layer so as to extend in the Y-direction, and the lines are formed in the first line layer located above the buried interconnect layer so as to extend in the Y-direction.