Selective DRAM Precharge via Address Line Segmentation
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Solution Overview
Problem
The increasing speed of DRAM devices has led to difficulties in meeting stringent signal setup and hold timing requirements during command and address transmission, resulting in significant time penalties and bandwidth overhead, particularly due to the limitations of current command formats that often require multiple commands to specify only a portion of the DRAM device, leading to inefficiencies in precharge operations.
Innovation Solution
The solution involves a memory system that reduces the number of commands required for precharge operations by allowing more precise selection of banks through the use of additional address signal lines, enabling any combination of banks to be specified in a single precharge command, thereby reducing bandwidth requirements and optimizing access times.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple commands are used to specify portions of DRAM device, then command format flexibility is improved, but command transmission time and bandwidth overhead increase
Solution Approach 1:
The address space is segmented into bank selection bits and row/column address bits. By separating bank selection from the full address, the patent enables selective precharge of specific banks without requiring multiple commands. This segmentation allows a single command to target specific portions of the DRAM device, resolving the contradiction between command flexibility and transmission time.
Solution Approach 2:
The patent adds a new dimension to command formatting by incorporating bank selection bits directly into the command structure. This dimensional addition allows the command to simultaneously specify both the target bank and the row/column address, eliminating the need for sequential commands and reducing transmission overhead.
2Measurement precision
If multiple commands are used for precharge operations, then precision in selecting DRAM portions is improved, but bandwidth overhead increases
Solution Approach 1:
The patent merges bank selection functionality with the address command structure by integrating bank selection bits into the command format. This merging allows a single command to simultaneously perform both address specification and bank selection, achieving precise bank targeting without the bandwidth overhead of multiple separate commands.
Solution Approach 2:
The command format is designed to be universal, handling both full-device operations and selective bank operations through the same command structure. By making the command format multi-functional, the patent eliminates the need for specialized multiple commands, thereby reducing bandwidth overhead while maintaining precision in bank selection.
3Speed
If double-clocking is implemented for faster interfaces, then data transfer speed is improved, but signal setup and hold timing requirements become more stringent
Solution Approach 1:
The patent performs preliminary bank selection before the actual data transfer operation. By selecting the target bank in advance using the integrated bank selection bits, the system prepares the DRAM device in a known state before the high-speed data transfer begins. This preliminary action reduces the timing sensitivity during the critical data transfer phase, allowing double-clocking to proceed reliably.
Data Source
AI summary
Apparatus and method for using a precharge command in which a plurality of address lines are individually used to specify which banks of memory cells within a memory device have an open row that is to be closed.