Bit-cell Voltage Distribution Sequencing for Read Disturb Prevention
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Solution Overview
Problem
Bit-cells in memory devices are prone to read disturb errors due to unstable voltage connections, where the word line is connected to operating voltage before the bit-cell, potentially destroying data values, and process variations exacerbate this issue.
Innovation Solution
A bit-cell voltage distribution system where the bit-cell circuit receives the operating voltage before the word line signal, using a voltage distribution circuit to connect the bit-cell voltage circuit to the word line driver circuit, ensuring the bit-cell operates with the necessary voltage before receiving the word line signal, thus preventing read disturb errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the word line is connected to operating voltage before the bit-cell, then the word line driver circuit can operate, but read disturb errors occur and data values are destroyed
Solution Approach 1:
The patent applies preliminary action by ensuring the bit-cell is connected to operating voltage before the word line driver circuit receives the operating voltage. This sequencing prevents read disturb errors by establishing proper voltage conditions in advance, eliminating the need for safety margin delays and improving read operation speed.
2Reliability
If safety margin delays are added to prevent read disturb errors, then data integrity is protected, but read response timing is degraded
Solution Approach 1:
The patent eliminates safety margin delays by implementing preliminary action through controlled voltage sequencing. The bit-cell receives operating voltage before the word line driver circuit, ensuring proper operation without requiring additional delay time, thus improving read response time while maintaining data integrity.
3Productivity
If the bit-cell receives operating voltage after the word line signal, then faster read operations are possible, but read disturb errors increase
Solution Approach 1:
The patent implements preliminary action by reversing the traditional voltage sequencing. The bit-cell is connected to operating voltage before the word line driver circuit operates, establishing stable voltage conditions in advance. This prevents read disturb errors and improves bit-cell stability while maintaining fast read operation speed.
4Speed
If process variations cause word line signals to propagate faster than bit-cell voltage, then read operations are faster, but read disturb errors are exacerbated
Solution Approach 1:
The patent addresses process variations by implementing preliminary action through controlled voltage sequencing. By ensuring the bit-cell receives operating voltage before the word line signal propagates, the patent compensates for variations in signal propagation speed and prevents read disturb errors, maintaining reliability despite speed variations.
Data Source
AI summary
In some embodiments, a method includes receiving, at a voltage distribution circuit, a power enable signal. In response to the power enable signal, the voltage distribution circuit may connect a word line driver circuit to a bit-cell voltage circuit such that an operating voltage is received at a bit-cell circuit before a word line signal form the word line driver circuit is received at the bit-cell circuit, where the operating voltage is provided by the bit-cell voltage circuit. The method may further include the bit-cell circuit providing the operating voltage along a bit line based on a data stored at the bit-cell circuit and based on the word line signal. In some embodiments, a static noise margin of one or more portions of the bit-cell circuit may be improved. Additionally, in some cases, a wakeup time of the bit-cell circuit may be ignored, resulting in a faster read operation.