Memory Bitline Precharge Drive Fight Current Using Multiple Power Domains
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Solution Overview
Problem
Semiconductor memory systems face challenges in achieving efficient power, performance, and stability tradeoffs due to the need for balancing multiple voltage and timing requirements, which often result in increased power consumption and reduced stability during memory access operations.
Innovation Solution
The use of a memory system with macro cells that employ different voltage supplies for bit cells and logic portions, where the bit cells receive word line inputs from a first voltage supply and the logic portion uses additional precharge logic driven by a second power supply, aligning the timing of access operations to prevent concurrent driving of voltage values on bit lines, thereby reducing power consumption and improving stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multiple voltage supplies are used for bit cells and logic portions, then power consumption is reduced and stability is improved, but device complexity increases
Solution Approach 1:
The memory macro cell is segmented into two distinct voltage domains: bit cells operate on a first voltage supply (VDD1) while logic portions operate on a second voltage supply (VDD2). This segmentation allows independent optimization of power consumption and stability for each component, resolving the contradiction by reducing overall power loss while maintaining manageable device complexity through modular design.
Solution Approach 2:
Different voltage supplies are applied to different portions of the memory macro cell based on their specific requirements. Bit cells receive VDD1 optimized for storage stability, while logic portions receive VDD2 optimized for switching performance. This local quality approach reduces power consumption in each region while maintaining overall system functionality.
2Reliability
If precharge logic is added to align timing, then stability and power efficiency improve, but device complexity increases
Solution Approach 1:
Precharge logic is implemented in the logic portion to align the timing of bit line precharging with the access operations in bit cells. This preliminary action ensures that bit lines are properly prepared before access operations begin, improving stability and preventing concurrent voltage driving while adding only necessary timing control functionality.
3Loss of energy
If timing alignment is achieved between bit cells and logic portion, then power consumption reduces, but manufacturing precision requirements increase
Solution Approach 1:
The patent changes the voltage parameter (using different voltage supplies VDD1 and VDD2) to achieve timing alignment between bit cells and logic portions. This parameter change allows independent timing control without requiring extremely tight manufacturing tolerances, thus reducing power consumption while maintaining feasible manufacturing precision requirements.
Data Source
AI summary
A system and method for efficient power, performance and stability tradeoffs of memory accesses are described. A memory includes an array of cells for storing data and a sense amplifier for controlling access to the array. The cells receive word line inputs for data access driven by a first voltage supply. The sense amplifier includes first precharge logic, which receives a first precharge input driven by the first power supply used by the array. Therefore, the first precharge input has similar timing characteristics as the word line input used in the array. The sense amplifier includes second precharge logic, which receives a second precharge input driven by a second power supply not used by the array and provides precharged values on bit lines driven by the second power supply.