Memory Power Management via Wake-Sleep Cycles
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Solution Overview
Problem
Current power management strategies for computer memory, such as self-refresh mode, result in significant power savings but incur performance penalties due to time-consuming power-up procedures, which are not suitable for systems with unpredictable memory access patterns.
Innovation Solution
Implementing a method to manage power in memory modules by maintaining a set of access requests and selectively switching DIMMs between low- and high-power states, allowing for efficient power usage while minimizing performance impact by overlapping power-up delays with other processing tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If memory enters self-refresh mode to save power, then power consumption is reduced significantly, but access time increases due to power-up procedures
Solution Approach 1:
The system performs preliminary actions by maintaining a queue of pending memory access requests and keeping the memory controller in a ready state. When memory is in self-refresh mode, the controller can immediately process requests once memory awakens, rather than waiting for the system to detect and respond to access needs. This preliminary preparation minimizes the effective access time penalty.
Solution Approach 2:
The patent implements periodic wake-sleep cycles for memory modules, where memory alternates between self-refresh mode (sleep) and active mode (wake). The system monitors access patterns and schedules memory activation periodically based on queued requests, creating a rhythmic wake-sleep pattern that optimizes both power savings and access responsiveness.
2Speed
If multiple DIMMs are kept in high-power state to ensure fast access, then access speed is maintained, but overall power consumption increases
Solution Approach 1:
The patent segments the memory system into multiple independent DIMM modules, each capable of operating independently in low-power or high-power states. The memory controller manages each DIMM separately based on access patterns, allowing selective activation of only those DIMMs currently needed for processing, rather than keeping all DIMMs in high-power state simultaneously.
Solution Approach 2:
The system dynamically adjusts the power state of individual DIMM modules based on real-time access patterns and workload demands. The memory controller continuously monitors request queues and transitions DIMMs between sleep and active states as needed, creating a dynamic power management system that adapts to changing system conditions rather than maintaining a static power state.
3Use of energy by moving object
If memory is placed in low-power state, then power budget is reduced, but system performance degrades due to power-up delays
Solution Approach 1:
The system performs preliminary actions by maintaining a queue of pending memory access requests and keeping the memory controller in a ready state. When memory is in self-refresh mode, the controller can immediately process requests once memory awakens, rather than waiting for the system to detect and respond to access needs. This preliminary preparation minimizes the effective access time penalty.
Solution Approach 2:
The patent ensures continuity of useful action by maintaining the memory controller in an active, ready state even when memory modules are in low-power mode. The controller continuously monitors for access requests and can immediately initiate memory activation when needed, ensuring that the useful action of request processing continues without interruption or significant delay.
Data Source
AI summary
A method of managing power states of memory modules while performing memory access operations is disclosed. Memory modules are in a power saving state until an access operation involving the module is to be performed. The module is placed in an operational mode, then the access operation is performed, then the module is returned to the power saving state. Apparatus and systems using the method are also disclosed and claimed.