Shared ECC Circuit for Memory Array Data Retention
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Solution Overview
Problem
The reduction in size of floating gate transistors in flash memory has led to a decline in data retention reliability, as the smaller volume affects the ability to store data effectively.
Innovation Solution
A memory array design that includes multiple memory blocks with shared error checking and correction (ECC) circuits and well taps, where word lines are connected to signal lines through contact regions, optimizing the layout to improve data retention reliability and reduce the occupied area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the volume of floating gate transistor is reduced to evolve flash memory to newer generations, then the storage density is improved, but the data retention reliability deteriorates
Solution Approach 1:
The patent combines multiple ECC circuits into a single shared ECC circuit that serves multiple memory blocks. This merging approach reduces the total area occupied by ECC circuits while maintaining error correction capabilities across all memory blocks, thereby improving storage density without sacrificing data retention reliability.
Solution Approach 2:
The shared ECC circuit is designed to handle error correction for multiple memory blocks universally. Instead of having dedicated ECC circuits for each memory block, the single ECC circuit performs error checking and correction across all memory blocks, optimizing area usage while preserving reliability.
2Reliability
If separate ECC circuits are provided for each memory block, then the data retention reliability is improved, but the occupied area increases
Solution Approach 1:
Multiple ECC circuits are merged into a single shared ECC circuit that serves all memory blocks. This consolidation reduces the total area occupied by ECC circuits while maintaining the error correction functionality across all memory blocks through shared resources.
Solution Approach 2:
The shared ECC circuit is designed with universal functionality to handle error correction for any memory block. It can selectively process errors from different memory blocks, providing reliable error correction across the entire memory array without requiring separate dedicated circuits for each block.
3Reliability
If more ECC circuit regions are distributed across memory blocks, then the data retention reliability is improved, but the wafer area usage efficiency deteriorates
Solution Approach 1:
The patent merges ECC circuit regions into a single shared location that serves all memory blocks. This consolidation improves wafer area usage efficiency by eliminating redundant ECC circuit instances while maintaining comprehensive error correction coverage across all memory blocks through the shared ECC circuit.
Solution Approach 2:
The shared ECC circuit region is designed to universally serve all memory blocks, providing error correction functionality across the entire array from a single location. This multi-functional design maximizes wafer area usage efficiency while ensuring data retention reliability for all memory blocks.
Data Source
AI summary
A memory array is provided. The memory array includes multiple memory blocks, each including multiple data storage regions and multiple groups of word lines. Each group of word lines extend across one of the memory blocks. The groups of word lines are connected to multiple overlying signal lines through multiple groups of first word line contact regions in the memory blocks and multiple second word line contact regions between the memory blocks.