Dual Rail SRAM Voltage Domain Segmentation
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Solution Overview
Problem
Dual rail SRAM architectures face challenges in reducing memory leakage power while maintaining fast access times, as increased voltage differences can lead to increased leakage and noise, and existing designs often result in read errors due to lag between word line disable and sense amplifier enable.
Innovation Solution
Operating word lines in a high voltage domain and bit lines in a low voltage domain, with a level shifter to maintain static noise margin and write margin, and minimizing the lag time between word line disable and sense amplifier enable to reduce read errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the memory array is operated in a high voltage domain to reduce leakage power, then leakage power is reduced significantly, but memory access time is impacted
Solution Approach 1:
The patent divides the SRAM system into two separate voltage domains: a high voltage domain for the memory array and a low voltage domain for the logic circuitry. This segmentation allows each domain to operate at its optimal voltage level, enabling the memory array to achieve low leakage power at high voltage while the logic operates efficiently at low voltage, thus resolving the contradiction between leakage reduction and access speed.
Solution Approach 2:
The patent introduces level shifters as intermediary components that interface between the high voltage memory array domain and the low voltage logic domain. These level shifters enable efficient signal translation and transfer between domains, ensuring that the memory access speed is not degraded despite the voltage domain separation, thereby resolving the contradiction between leakage power reduction and access time.
2Loss of energy
If the voltage difference between high voltage and low voltage domains is increased to gain more leakage reduction, then leakage power reduction increases, but read errors increase due to lag between word line disable and sense amplifier enable
Solution Approach 1:
The patent implements preliminary action by pre-charging the bit lines to the appropriate voltage level before the word line is disabled. This ensures that when the word line transitions from high to low voltage, the sense amplifier is already prepared with the correct voltage conditions, eliminating the race condition and preventing read errors even with large voltage domain differences.
Solution Approach 2:
The patent employs feedback mechanisms in the sense amplifier design that monitor the voltage conditions and adjust the amplification timing accordingly. This feedback ensures that the sense amplifier enables at the optimal moment after word line disable, maintaining reliable read operations despite the voltage difference between domains and preventing read errors.
Data Source
AI summary
An SRAM device has a voltage input terminal configured to receive a first signal at a first voltage level. A level shifter is connected to the voltage input terminal to receive the first signal, and the level shifter is configured to output a second signal at a second voltage level higher than the first voltage level. A memory cell has a word line and a bit line. The word line is connected to the output terminal of the level shifter to selectively receive the second signal at the second voltage level, and the bit line is connected to the voltage input terminal to selectively receive the first signal at the first voltage level. A sense amplifier is connected to the bit line and is configured to provide an output of the memory cell. The sense amplifier has a sense amplifier input connected to the output terminal of the level shifter to selectively receive the second signal at the second voltage level.