Neuromorphic Synapse Blocks Sharing Logic Element
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Solution Overview
Problem
Current neuromorphic devices require multiple logic elements for each synapse block, leading to increased complexity and size, which hinders efficient data processing and pattern recognition.
Innovation Solution
A neuromorphic device design where multiple synapse blocks share a common logic element, allowing for simplified circuitry and reduced chip size by using a single logic circuit for all synapse blocks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple logic elements are used for each synapse block, then each synapse block can operate independently with dedicated processing, but the device complexity and chip size increase significantly
Solution Approach 1:
A single logic element is designed to serve multiple synapse blocks through time-division multiplexing. The logic element sequentially processes signals from different synapse blocks in different time slots, enabling one logic element to perform the function that would traditionally require multiple dedicated logic elements. This reduces overall device complexity while maintaining the operational independence of each synapse block.
Solution Approach 2:
The patent introduces a synapse signal selector that segments the signal processing function across time. Instead of having simultaneous dedicated logic elements for each synapse block, the system segments the processing time and uses a single logic element to handle different synapse blocks in sequence. This temporal segmentation resolves the contradiction by maintaining functional independence while reducing hardware complexity.
2Productivity
If multiple logic elements are allocated to each synapse block, then processing capability is maintained, but the chip size and manufacturing cost increase
Solution Approach 1:
The logic element is designed as a universal component that can process signals from any synapse block through time-division multiplexing control. This multi-functional design eliminates the need for multiple dedicated logic elements, significantly reducing the chip area while preserving the data processing capability through sequential operation of the single shared logic element.
Solution Approach 2:
The patent transitions from a spatial allocation model (multiple logic elements simultaneously distributed across the chip) to a temporal allocation model (single logic element operating sequentially across time). This dimensional shift from space to time allows the system to maintain processing capability while dramatically reducing the physical footprint on the chip.
3Device complexity
If a single logic element is shared by all synapse blocks, then device complexity and chip size are reduced, but signal processing time and interference may increase
Solution Approach 1:
The synapse signal selector divides the processing timeline into distinct time slots, assigning each synapse block a dedicated slot for signal transmission to the shared logic element. This temporal segmentation ensures that signal processing occurs sequentially without interference between different synapse blocks, preventing time loss while maintaining the benefits of hardware sharing.
Solution Approach 2:
The control unit implements feedback mechanisms to manage the time-division multiplexing schedule, coordinating the activation of different synapse blocks with the shared logic element. This feedback control ensures efficient time slot allocation and prevents conflicts, minimizing processing delays while maintaining system simplicity.
Data Source
AI summary
A neuromorphic device is disclosed. The neuromorphic device may include an input element; a synapse element having a plurality of synapse blocks; a logic element; and an output element. The plurality of synapse blocks may share the logic element.