Memory Device Error Detection Unit for Intermittent Failure Prevention
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Memory devices face intermittent failures due to charge leakage in cell capacitors, which are difficult to detect and correct, especially as integration increases and capacitance decreases, leading to irregular and hard-to-prevent data loss.
Innovation Solution
A memory device with an error detection unit that latches read data from selected memory cells, detects errors through a two-phase process, and corrects errors by writing back latched data, using a refresh counter, detection counter, flag signal generation unit, period signal generation unit, and error detection unit to enhance detection accuracy and prevent intermittent failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the degree of integration of memory devices is increased and the width of line patterns is decreased, then the density and capacity of memory devices are improved, but the capacitance of cell capacitor is reduced and the voltage difference for distinguishing data becomes smaller, leading to increased likelihood of 1-bit failure
Solution Approach 1:
The patent performs a preliminary read operation before the refresh operation to detect potential intermittent failures. By reading data from memory cells prior to refreshing, the system can identify cells that are about to fail due to charge leakage, allowing for corrective action before data loss occurs. This preliminary detection mechanism addresses the reliability issue arising from reduced capacitance in high-density memory cells.
2Productivity
If a typical refresh operation is performed on a constant cycle, then the memory device maintains normal operation, but it is difficult to prevent intermittent failure since such failures may occur during the refresh operation
Solution Approach 1:
The patent segments the refresh operation into two distinct phases: a first phase that performs read operations to detect intermittent failures, and a second phase that performs actual refresh operations. This segmentation allows the system to detect and address intermittent failures before they cause data loss, while maintaining the necessary refresh cycle for normal memory operation. The separated detection and refresh phases enable more reliable intermittent failure prevention without compromising refresh efficiency.
3Ease of repair
If conventional test and repair methods are used to detect and repair failed cells, then permanently failed cells can be repaired with redundancy cells, but intermittent failures that occur in non-detected memory cells cannot be prevented
Solution Approach 1:
The patent implements a feedback mechanism where read data from memory cells is continuously monitored and compared during the detection phase. When an intermittent failure is detected through data comparison, the system generates an error signal that triggers corrective actions. This feedback loop enables the system to dynamically respond to intermittent failures as they occur, rather than relying solely on conventional test and repair methods that only address permanently failed cells identified during manufacturing testing.
Data Source
AI summary
A memory device may include a plurality of memory cells; and an error detection unit suitable for latching first read data of one or more memory cells selected from the plurality of memory cells after refreshing the selected memory cells, in a first phase, and suitable for detecting errors of the selected memory cells before refreshing the selected memory cells, in a second phase.