Memory Cell Using Semiconductor Element for High-Density Stability
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Solution Overview
Problem
Existing memory devices using semiconductor elements face challenges in achieving high-density memory with stable operations, as they suffer from issues like undesired signal input to unselected cells during voltage application.
Innovation Solution
A memory cell configuration is proposed, featuring a first semiconductor region extending perpendicular to a substrate, surrounded by second and third semiconductor regions, with specific dielectric and gate conductor layers. This configuration allows for controlled voltage applications during write, read, and erase operations, minimizing interference between cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If 1TDRAM structure is used to achieve high density, then memory density is improved, but operation stability deteriorates due to undesired signals affecting unselected cells
Solution Approach 1:
The memory cell is divided into two separate transistors (first MOS transistor and second MOS transistor) instead of using a single transistor structure. Each transistor independently controls one bit of data, preventing signal interference between adjacent cells and improving operation stability while maintaining high density through the compact 2T configuration.
Solution Approach 2:
Different regions of the memory cell are assigned different semiconductor types (n-type and p-type regions) to create localized functional zones. The first MOS transistor uses n-type source/drain regions while the second uses p-type regions, enabling independent control and reducing cross-talk between selected and unselected cells.
2Quantity of substance
If three-dimensional stacking is implemented to increase density, then memory capacity is improved, but manufacturing complexity increases
Solution Approach 1:
The memory structure extends in the vertical direction with multiple semiconductor layers stacked above the substrate. Source/drain regions are formed at different heights (first source/drain at lower level, second source/drain at upper level), enabling three-dimensional integration that increases storage capacity while using standard semiconductor fabrication processes.
Solution Approach 2:
The second MOS transistor is positioned above and surrounds part of the first MOS transistor structure. The second gate electrode is arranged to surround the channel region from above, creating a nested configuration that maximizes space utilization and achieves high density without requiring complex manufacturing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed configuration enables high-density memory with improved stability by reducing unwanted signal interference and allowing for efficient erasure operations, thereby enhancing read margins and power consumption efficiency.
Implementation Method 1
among a hole group and an electron group produced by an impact ionization phenomenon in a channel by a source-drain electrical current of an n-channel MOS transistor
Data Source
AI summary
Provided is a memory semiconductor device in which a p-type semiconductor region is formed at an n+layer to which a bit line is connected, an n-type semiconductor layer to which a source line is connected is further formed, a first gate insulating layer and a first gate conductor layer to which a word line is connected exist, a second gate insulating layer and a second gate conductor layer to which a plate line is connected are provided, and a distance from the n+layer to the first gate conductor layer is smaller than a distance up to the second gate conductor layer. At the time of an erase operation, the plate line and the source line have a positive electric potential of the same polarity or have a voltage of 0 V.