Semiconductor Memory Subarray Isolation for High-Speed Data Reading
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor memory devices face challenges in achieving high-speed data reading due to the high load on internal data buses, which limits their ability to handle increased memory cell rows and columns efficiently, especially in SRAMs where the shared sense amplifier construction from DRAMs is not directly applicable.
Innovation Solution
The semiconductor memory device is designed with a plurality of memory blocks, each divided into subarrays, featuring a sense amplifier shared across these subarrays, with separate data lines and column selection circuits for each subarray, reducing the load on the sense amplifier and internal data bus by isolating the local data lines and connecting only the selected subarray to the sense amplifier, thereby reducing bit line load and enabling high-speed data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of memory cell rows and columns is increased to enhance storage capacity, then the memory device can store more data, but the load on internal data buses increases, limiting high-speed data reading capability
Solution Approach 1:
The memory device is divided into multiple memory blocks, each containing subarrays with dedicated sense amplifiers. This segmentation allows parallel data reading operations across different blocks, maintaining high-speed performance while increasing overall storage capacity. Each memory block operates independently with its own sense amplifier, preventing bus load bottlenecks.
2Device complexity
If a shared sense amplifier construction from DRAMs is applied to SRAM, then device complexity is reduced, but the load on the sense amplifier and internal data bus increases, preventing high-speed data reading
Solution Approach 1:
Each sense amplifier is designed to serve multiple subarrays within its memory block, providing multi-functionality. The sense amplifier can selectively connect to different subarrays through column selection circuits, achieving universality without creating bottlenecks. This allows a single sense amplifier to handle data from multiple subarrays while maintaining high-speed performance through selective activation.
3Productivity
If separate data lines are provided for each subarray to reduce sense amplifier load, then data reading speed is improved, but chip layout area increases
Solution Approach 1:
Data lines from multiple subarrays within the same memory block are merged and shared through common internal data buses. This merging reduces the total number of separate data lines required, decreasing chip layout area while maintaining high-speed performance through the parallel architecture of multiple memory blocks.
Data Source
AI summary
Each of a plurality of memory blocks arranged for 1 bit data is divided into two subarrays. A separate local data line is provided for each subarray and coupled to a sense amplifier via an isolation gate. A memory cell is selected in a selected subarray of a selected memory block, and a bit line of the selected memory cell is coupled to a corresponding local data line. Only a local data line of the selected subarray is coupled to the sense amplifier to perform a sense operation, and a global read data line is driven via a read driver in accordance with an output signal of the sense amplifier. A load of a sense node of the sense amplifier in a semiconductor memory device is reduced to implement high-speed reading of internal data.