Semiconductor Memory 1T Cell with Shared Connection Layer
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high integration and efficient operation due to limitations in controlling electrical connections and managing resistance states in variable resistance elements.
Innovation Solution
The proposed semiconductor memory design incorporates first and second variable resistance elements, each with multiple terminals, and transistors to control electrical connections. A connection layer electrically connects the terminals of these elements, enabling efficient programming and reading operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional memory structures are used, then device functionality is achieved, but integration density is limited
Solution Approach 1:
The patent merges multiple functionality into a single memory cell structure by integrating two variable resistance elements with shared transistor control. The first variable resistance element (R1) and second variable resistance element (R2) are connected such that they share common terminals and control mechanisms, enabling one cell to store multiple bits of data. This combining approach directly increases integration density while maintaining data storage efficiency.
Solution Approach 2:
The memory cell structure achieves multi-functionality by enabling the same physical structure to perform multiple operations: storing multiple bits of data, supporting read operations for different elements, and providing selective access through shared transistor control. The connection layer and shared terminals allow the structure to serve multiple purposes within a single cell, improving both integration density and data storage efficiency.
2Productivity
If more variable resistance elements are added to increase storage capacity, then data storage efficiency improves, but interference between elements increases
Solution Approach 1:
The patent segments the control of variable resistance elements by introducing separate transistors (first transistor and second transistor) that independently control access to the first variable resistance element (R1) and second variable resistance element (R2) respectively. This segmentation allows selective programming and reading of individual elements without affecting others, thereby reducing interference while maintaining high data storage efficiency.
Solution Approach 2:
The connection layer acts as an intermediary structure that electrically connects the second terminal of the first variable resistance element to the second and third terminals of the second variable resistance element. This intermediary connection enables shared access paths while maintaining electrical isolation through the transistor control mechanisms, allowing multiple elements to coexist without mutual interference.
3Ease of operation
If transistor control is added to manage variable resistance elements, then electrical connection control improves, but device complexity increases
Solution Approach 1:
The patent merges control functions by having transistors share common structures and connection paths. The first transistor and second transistor are integrated into the same memory cell structure with shared source/drain regions and interconnect layers. This merging reduces the overall complexity compared to fully separate control structures while maintaining precise electrical connection control for multiple variable resistance elements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design allows for high integration of memory devices by implementing a 1T memory cell structure, which improves data storage efficiency and reduces power consumption while minimizing interference between variable resistance elements.
Implementation Method 1
memory devices that can store data by switching between different resistance states according to an applied voltage or current
Data Source
AI summary
A semiconductor memory may include: a first variable resistance element including a first terminal and a second terminal; a second variable resistance element including a first terminal, a second terminal, and a third terminal; a first transistor configured to control an electrical connection between a first conductive line and the first terminal of the first variable resistance element; a second transistor configured to control an electrical connection between the first conductive line and the first terminal of the second variable resistance element; a connection layer structured to electrically connect the second terminal of the first variable resistance element to the second and third terminals of the second variable resistance element; and a third conductive line is electrically connected to the connection layer.