Wordline Voltage Generator for Semiconductor Memory Devices
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Solution Overview
Problem
Conventional semiconductor memory devices experience data loss and deteriorated refresh performance due to leakage currents generated by gate-induced drain leakage (GIDL) when using negative wordline voltages, especially in high integration density and high-speed operations.
Innovation Solution
A semiconductor memory device with a wordline voltage generator that supplies a first negative voltage during standby and a second lower negative voltage during refresh operations, utilizing a wordline driver and negative voltage generator with PMOS and NMOS transistors, and a level detector to detect and amplify voltage levels for optimal voltage supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a negative voltage is applied to the wordline to maintain logic low level, then the transistor is kept off, but gate-induced drain leakage (GIDL) current is generated causing data loss
Solution Approach 1:
The patent applies dynamics by making the wordline voltage adjustable rather than fixed. The wordline voltage generator dynamically switches between a first negative voltage (VBB1) during standby and a second negative voltage (VBB2) during refresh operations. This dynamic voltage adjustment allows the system to optimize between maintaining transistor off-state and minimizing GIDL leakage current, thereby resolving the contradiction between reliability and data loss.
Solution Approach 2:
The patent changes the voltage parameter of the wordline based on operational state. By applying a first negative voltage level during standby and switching to a second negative voltage level during refresh operations, the system modifies the electrical parameter to balance transistor control and leakage suppression. This parameter change approach directly addresses the GIDL-induced data loss while maintaining proper transistor operation.
2Loss of energy
If the threshold voltage of the access transistor is increased to suppress current leakage, then leakage is reduced, but device reliability deteriorates due to higher integration density and voltage level effects
Solution Approach 1:
Instead of changing the transistor's threshold voltage parameter, the patent changes the wordline voltage parameter applied to the gate. By adjusting the negative voltage level on the wordline between standby and refresh modes, the system achieves leakage suppression without modifying the transistor's inherent threshold voltage, thereby preserving device reliability under high integration density conditions.
3Device complexity
If a single negative voltage is applied to the wordline during both standby and refresh operations, then the circuit is simple, but refresh performance deteriorates due to GIDL leakage
Solution Approach 1:
The patent introduces dynamics into the voltage generation system by implementing a wordline voltage generator that switches between two negative voltage levels based on operational mode. During standby, a first negative voltage is applied; during refresh operations, a second negative voltage is applied. This dynamic approach maintains circuit simplicity while significantly improving refresh performance by reducing GIDL leakage current.
Data Source
AI summary
A semiconductor memory device that includes a memory cell connected to a wordline and a wordline voltage generator. The wordline voltage generator supplies a first negative voltage to the wordline in a standby state and supplies a second negative voltage that is lower with respect to ground than the first negative voltage to the wordline in a refresh operation. Accordingly, a leakage current generated at a transistor of a memory cell by gate-induced drain leakage (GIDL) is suppressed to enhance the performance of a refresh operation.