Smart Memory Module Computing Functions
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Solution Overview
Problem
Smart memory circuits often require processor intervention for data manipulation, leading to inefficient data exchange and increased processor workload due to missing or improperly stored data, which can slow down computing operations.
Innovation Solution
A memory device with a control circuit to break down instructions into elementary operations, a direct data transfer circuit for internal memory access, and an arbitration circuit to manage simultaneous requests using predefined priority rules, along with a wider internal data link to enhance data transfer efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data are not present in the smart memory or not stored in the desired space, then processor intervention is required for data manipulation, but this increases processor workload and slows down computing operations
Solution Approach 1:
The patent segments the memory device into multiple independent control circuits (first control circuit, second control circuit, third control circuit) that can operate autonomously. Each control circuit handles specific data manipulation tasks without requiring processor intervention, thereby reducing processor workload while maintaining high computing operation speed.
Solution Approach 2:
The memory device implements self-service through multiple control circuits that autonomously manage data operations. The first control circuit performs read operations, the second control circuit performs write operations, and the third control circuit performs compute operations, all without processor involvement, enabling the system to serve itself and eliminate the need for external processor intervention.
2Ease of operation
If processor orchestrates read/write operations for data manipulation, then data can be accessed and manipulated, but this increases data exchange channel usage and processor workload
Solution Approach 1:
The patent divides data access operations into three separate control circuits, each dedicated to a specific function (read, write, compute). This segmentation allows data to be accessed and manipulated through specialized circuits that operate independently of the processor, reducing data exchange channel usage while maintaining ease of operation.
Solution Approach 2:
The control circuits act as intermediaries between the processor and the memory array. Instead of the processor directly orchestrating read/write operations, the control circuits mediate these operations, handling data manipulation tasks autonomously and reducing the burden on data exchange channels.
3Productivity
If multiple control circuits operate autonomously without arbitration, then each circuit can execute operations independently, but simultaneous requests would cause conflicts in memory access
Solution Approach 1:
The arbitration circuit serves as an intermediary that manages simultaneous requests from multiple control circuits. It receives requests from the first, second, and third control circuits, applies priority rules to determine execution order, and ensures conflict-free memory access while maintaining parallel operation capability.
Solution Approach 2:
The arbitration circuit changes the execution parameter of simultaneous requests by applying priority rules. It dynamically determines which control circuit's request is executed first based on predefined priorities, transforming multiple simultaneous requests into a sequenced execution pattern that prevents conflicts while maintaining high productivity.
Data Source
AI summary
The present description concerns a memory device (200) comprising: a memory circuit (201) implementing operations and performing elementary operations including a reading, a writing, or a computing operation; a control circuit (205) receiving instructions from a processor (231), and breaking down each received instruction into a plurality of elementary operations to generate an elementary operation request flow; a circuit (203) of direct data transfer from or to said memory circuit (201), the transfer circuit (203) receiving instructions from the processor (231), breaking down each received instruction into a plurality of elementary operations to be performed in said memory circuit to generate an elementary operation request flow; an internal data exchange link (204) directly coupling said memory circuit (201) to the direct transfer circuit (203); and an arbitration circuit (309).