Word Line Driver Pull-Down Transistor for Read Disturb Mitigation
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Solution Overview
Problem
Conventional techniques for mitigating read disturb in machine memory, such as those using shunt transistors on word line driver circuits, are unreliable due to process, temperature, and voltage variations, and exhibit operational deficiencies in six-transistor SRAM and eight-transistor cells, leading to read and write failures.
Innovation Solution
Implementing a pull-down transistor that tracks operational changes in word line drivers, reducing stability issues by providing a discharging path for the word line and mitigating read disturb effects across multiple memory cells, while also reducing circuit area and improving manufacturing yield.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If conventional shunt transistors are used on word line driver circuits to mitigate read disturb, then read disturb mitigation is attempted, but reliability deteriorates due to process, temperature, and voltage variations
Solution Approach 1:
A new word line driver circuit is introduced as an intermediary component between the existing word line and memory cells. This new driver incorporates a pull-down transistor that actively controls the word line voltage, mediating the interaction between the memory cells and the rest of the system. The pull-down transistor serves as a mediator that prevents direct harmful interaction by providing a controlled discharge path, thereby mitigating read disturb while maintaining reliability across process, temperature, and voltage variations.
2Area of stationary object
If six-transistor SRAM structure is used to achieve compact memory, then memory density is improved, but operational deficiencies occur including read failure and write half-select disturbance
Solution Approach 1:
The invention changes the voltage parameters of the word line dynamically during read and write operations. By adjusting the word line voltage level and timing, the circuit compensates for the inherent vulnerabilities of the 6T SRAM structure. The pull-down transistor modifies the voltage waveform to prevent read failure caused by insufficient voltage division and to eliminate write half-select disturbance, thereby improving operational reliability without increasing cell area.
3Object-affected harmful factors
If word line lowering technique is implemented by adding pull-down transistor to correct read disturb, then read disturb is mitigated, but device complexity and area increase
Solution Approach 1:
The invention merges the pull-down transistor functionality directly into the word line driver circuit, combining multiple functions into a single integrated unit. The new word line driver incorporates the pull-down transistor along with the existing driver transistors, sharing common components and control signals. This merging approach mitigates read disturb while minimizing the increase in device complexity and area, as the pull-down transistor shares the word line connection and control infrastructure with the existing driver circuit.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively mitigates read disturb effects in both full-selected and half-selected memory cells, improving the reliability of read and write operations across varying conditions and enhancing manufacturing yield by stabilizing word line drivers and reducing transient voltage fluctuations.
Implementation Method 1
providing a discharging path for the word line
Implementation Method 2
the data '0' storage node rises to a certain voltage higher than the ground, according to the voltage dividing across the access transistor and the drive transistor
Data Source
AI summary
A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.