Semiconductor Memory Device Variable Access Time Control
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Solution Overview
Problem
Semiconductor memory devices face challenges in maintaining access performance at high frequencies due to insufficient margin for input/output data caused by jitter and noise, which is exacerbated by the need to balance tCCD values between ensuring sufficient data transmission and maintaining processing efficiency.
Innovation Solution
A semiconductor memory device with a cell array and sense amplifier that adjusts pulse widths of write-in and read-out data in accordance with a variable access time, allowing for longer first access times as operation frequency increases, enabling efficient command processing and data transmission without degrading performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If tCCD is fixed to a larger value (4tCK) to ensure sufficient margin for input/output data, then reliability of data transmission is improved, but productivity (access performance) deteriorates due to lengthened delay time for accessing bank groups
Solution Approach 1:
The patent applies dynamics by making tCCD variable rather than fixed. The control circuit dynamically adjusts tCCD based on the operation frequency: at higher frequencies where jitter and noise are more problematic, tCCD is increased to ensure reliable data transmission; at lower frequencies, tCCD can be reduced to improve access performance. This dynamic adaptation resolves the contradiction between reliability and productivity.
Solution Approach 2:
The patent changes the parameter tCCD from a fixed value to a variable value that adapts to operating conditions. By modifying tCCD based on frequency requirements, the system can optimize both reliability (sufficient margin at high frequencies) and productivity (faster access at lower frequencies), resolving the technical contradiction.
2Productivity
If operation frequency is increased to improve productivity, then speed of data transmission is improved, but reliability deteriorates due to narrower clock width causing insufficient margin for input/output data
Solution Approach 1:
The system dynamically adjusts tCCD in response to operation frequency changes. When frequency increases and clock width narrows, the control circuit increases tCCD to provide sufficient margin for reliable data transmission. This dynamic response allows the system to maintain reliability across different operating frequencies while maximizing productivity.
Solution Approach 2:
The control circuit uses feedback from the operation frequency to automatically adjust tCCD. The system monitors the operating conditions and modifies tCCD accordingly, creating a closed-loop control mechanism that ensures reliability is maintained even as productivity increases through higher frequencies.
Data Source
AI summary
Example embodiments provide a semiconductor memory device that may include: a cell array arranged in pluralities of rows and columns; and a sense amplifier conducting writing and reading operations to the cell array in response to writing and reading commands in correspondence with an access time, which may be variable in period. The sense amplifier adjusts pulse widths of write-in and read-out data in accordance with a period of the access time.