Hierarchical Neural Network Storage with ECC and Non-ECC Memory Segmentation
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Solution Overview
Problem
Large-scale neural network parameters require significant storage capacity and energy consumption for memory access, and existing error correcting code (ECC) memories add overhead in storage and computation, ignoring the fault-tolerant capabilities of neural networks.
Innovation Solution
Implementing a hierarchical storage system with an ECC memory for important bits and a non-ECC memory for unimportant bits of neural network parameters, using 4T or 3T SRAMs to reduce storage overhead and energy consumption while leveraging fault-tolerant capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If ECC memory is used to store neural network parameters, then data reliability is improved, but storage capacity overhead and memory access power consumption increase
Solution Approach 1:
The patent segments neural network parameters into important bits and unimportant bits, storing them in different memory types. Important bits requiring high reliability are stored in ECC memory, while unimportant bits are stored in non-ECC memory, thus reducing overall storage overhead while maintaining necessary data reliability.
Solution Approach 2:
The patent applies different storage quality levels to different parts of the data. Critical parameters (important bits) receive full ECC protection, while non-critical parameters (unimportant bits) use simpler storage, optimizing the balance between reliability and resource consumption.
2Reliability
If ECC memory is used to store neural network parameters, then data reliability is improved, but memory access power consumption increases
Solution Approach 1:
The patent divides parameters into important and unimportant bits, accessing ECC memory only for important bits. This segmentation reduces the frequency and volume of high-power ECC memory accesses, thereby lowering overall power consumption while maintaining reliability for critical operations.
Solution Approach 2:
Different power consumption levels are applied locally based on data importance. Accessing unimportant bits from non-ECC memory consumes less power, while important bits access ECC memory when reliability is required, optimizing the power-reliability tradeoff.
3Reliability
If all parameters are stored in ECC memory, then fault tolerance is improved, but computation overhead increases
Solution Approach 1:
The patent segments parameters into important and unimportant bits, applying ECC protection only to important bits. This reduces the computation overhead of error correction while maintaining fault tolerance for critical parameters that require it.
Solution Approach 2:
Different levels of fault tolerance are applied locally based on parameter importance. Critical parameters receive full ECC protection and error checking, while unimportant parameters use minimal or no error correction, reducing overall computational overhead.
Data Source
AI summary
Aspect for storage device with fault tolerance capability for neural networks are described herein. The aspects may include a first storage unit of a storage device. The first storage unit is configured to store one or more first bits of data and the data includes floating point type data and fixed point type data. The first bits include one or more sign bits of the floating point type data and the fixed point type data. The aspect may further include a second storage unit of the storage device. The second storage unit may be configured to store one or more second bits of the data. In some examples, the first storage unit may include an ECC memory and the second storage unit may include a non-ECC memory. The ECC memory may include an ECC check Dynamic Random Access Memory and an ECC check Static Random Access Memory.