Adjusting Drain Bias in NROM Cells to Reduce Second Bit Effect
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Solution Overview
Problem
The second bit effect in charge trapping memory cells, such as NROM, limits the available threshold voltage window, causing data stored at different parts of the nitride storage layer to affect each other, leading to reduced read accuracy and increased risk of read disturb during reverse read operations.
Innovation Solution
An integrated circuit with a nonvolatile memory cell and control circuitry that applies a read bias arrangement based on the data stored in both the addressed and neighboring bits, adjusting the voltage applied to the current carrying terminals to reduce the second bit effect and prevent read disturb, by raising the voltage if the threshold voltage exceeds a minimum threshold and applying a lower voltage otherwise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If increased voltage magnitude is applied during reverse read operation, then the second bit effect is reduced, but read disturb effect increases causing unwanted programming of neighboring bit
Solution Approach 1:
The patent applies different voltage magnitudes during reverse read operations based on the data state of the neighboring bit. When the neighboring bit stores data representing a high threshold voltage, a higher voltage magnitude is applied to reduce the second bit effect and improve read accuracy. When the neighboring bit stores data representing a low threshold voltage, a lower voltage magnitude is applied to prevent read disturb effect. This dynamic parameter adjustment resolves the contradiction by adapting the voltage level to the specific data state.
2Reliability
If the neighbor bit stores high threshold voltage data, then the second bit effect is reduced, but the reverse read current is reduced limiting the available threshold voltage window
Solution Approach 1:
The patent dynamically adjusts the voltage magnitude applied during reverse read operations based on the data state of the neighboring bit. This dynamic approach allows the system to optimize between reducing the second bit effect and maintaining sufficient read current. By adapting the voltage level to the neighboring bit's state, the system can achieve better separation of threshold voltage windows while maintaining adequate read current margins.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach widens the threshold voltage window, allowing multiple programmed threshold voltage ranges to correspond to the same sensed threshold voltage range, reducing the second bit effect and minimizing read disturb, thereby improving data storage and retrieval accuracy.
Implementation Method 1
Charge trapping memory cells such as NROM can be programmed at different localized parts of the silicon nitride storage layer by a mechanism such as channel hot electron (CHE) injection
Data Source
AI summary
The storage layer such as a nitride layer of a nonvolatile memory cell has two storage parts storing separately addressable data, typically respectively proximate to the source terminal and the drain terminal. The applied drain voltage while sensing the data of one of the storage parts depends on the data stored at the other storage part. If the data stored at the other storage part is represented by a threshold voltage exceeding a minimum threshold voltage, then the applied drain voltage is raised. This technology is useful in read operations and program verify operations to widen the threshold voltage window.