Power-On-Reset Circuit for Memory Array Word Line Control
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Solution Overview
Problem
Memory circuits often experience abnormal operations due to premature activation of word lines caused by latch circuits starting in the wrong state during power-on, leading to high currents and undesirable behavior.
Innovation Solution
A power-on-reset circuit is implemented to deactivate predecoded address lines upon powering on, ensuring all word lines are deactivated, preventing high currents and normalizing memory array operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If latch circuits are used in the address predecoder for synchronous activation of word lines, then the memory circuit can operate with precise timing control, but the latch circuits may start up in the wrong state during power-on causing premature word line activation and high currents
Solution Approach 1:
The power-on-reset circuit performs preliminary action by resetting the latch circuits to a known state before normal operation begins. The reset signal is generated immediately upon power-on detection, ensuring that any premature word line activation is prevented before it can cause harmful effects.
Solution Approach 2:
The power-on-reset circuit applies preliminary anti-action by generating a reset signal that actively counteracts any incorrect state that may occur during power-on. This reset signal deactivates any prematurely activated word lines and resets the latch circuits to their initial state, preventing the harmful effects of incorrect startup states.
2Loss of time
If predecoded address lines are activated during power-on to enable memory access, then the memory circuit can begin operation quickly, but high currents may flow through the memory array causing abnormal operation
Solution Approach 1:
The power-on-reset circuit performs preliminary action by detecting the power-on state and generating a reset signal before normal memory access operations begin. This ensures that the latch circuits are in a known good state and prevents premature word line activation that would cause high currents.
Solution Approach 2:
The power-on-reset circuit acts as an intermediary between the power-on event and the address predecoder. It monitors the power-on state and controls the reset signal generation, mediating between the power supply and the latch circuits to prevent incorrect states while enabling quick operation.
3Productivity
If the address predecoder activates word lines based on input addresses during normal operation, then memory cells can be accessed efficiently, but latch circuits may remain in incorrect states causing continuous high currents
Solution Approach 1:
The power-on-reset circuit implements feedback by monitoring the state of the latch circuits and the power-on condition. When it detects that power has been applied and that latch circuits may be in incorrect states, it generates a reset signal to correct the state, ensuring continuous reliable operation during memory access.
Solution Approach 2:
The power-on-reset circuit performs periodic state verification and resetting. The reset signal is generated periodically or continuously during power-on to ensure that latch circuits remain in correct states, preventing continuous high current conditions while maintaining efficient memory access operation.
Data Source
AI summary
The disclosure relates to an apparatus for deactivating one or more predecoded address lines of a memory circuit in response to one or more of the predecoded address lines being activated upon powering on of at least a portion of the apparatus. In particular, the apparatus includes a memory device; an address predecoder configured to activate one or more of a plurality of predecoded address lines based on an input address, wherein the plurality of predecoded address lines are coupled to the memory device for accessing one or more memory cells associated with the one or more activated predecoded address lines; and a power-on-reset circuit configured to deactivate one or more of the predecoded address lines in response to the one or more of the predecoded address lines being activated upon powering on the at least portion of the apparatus.