Semiconductor Device Multi-Mode Data Pattern Generation
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Solution Overview
Problem
Semiconductor devices face challenges in effectively testing memory cells due to the increasing demand for more data storage, requiring innovative methods to generate and test various data patterns across different operation modes.
Innovation Solution
A semiconductor device and system that can operate in multiple modes (serial, clock, and random) based on code signals, generating data with specific patterns to test memory cells by utilizing a data processing circuit and memory circuit configuration, including strobe signal generation, operation control, and pattern data generation circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a semiconductor device uses a larger number of memory cells to store more data, then data storage capacity is improved, but testing complexity and difficulty increase
Solution Approach 1:
The data processing circuit is designed to perform multiple functions: it can generate serial data patterns, clock patterns, and random patterns, and it can operate in both normal operation mode and test mode. This multi-functionality allows a single circuit to handle both data storage operations and comprehensive testing of memory cells, resolving the contradiction between increased storage capacity and testing complexity
Solution Approach 2:
The semiconductor device dynamically switches between different operation modes (normal mode and test modes) based on control signals. In test modes, the data processing circuit generates various test patterns (serial, clock, random) to systematically test memory cells. This dynamic operation allows the device to adapt its functionality based on operational requirements, enabling comprehensive testing without permanently increasing device complexity
2Measurement precision
If multiple test patterns are generated to thoroughly test memory cells, then measurement precision is improved, but device complexity increases
Solution Approach 1:
The patent combines multiple test pattern generation capabilities within a single data processing circuit. The circuit can generate serial patterns (where data bits follow a specific sequence), clock patterns (alternating 0s and 1s), and random patterns, all within one integrated structure. This merging of functions allows comprehensive testing with high measurement precision while avoiding the need for separate dedicated circuits for each test pattern type
Solution Approach 2:
The data processing circuit changes its operational parameters based on the selected test mode. By receiving control signals that indicate the desired test pattern type, the circuit dynamically adjusts its data generation behavior. This parameter-based control allows the same hardware circuit to produce different test patterns, achieving high test coverage without proportionally increasing circuit complexity
Data Source
AI summary
A semiconductor system including a semiconductor device configured to operate in various modes to generate output data having different patterns.