BIST Circuit Weight Select Logic for Fault Coverage
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Solution Overview
Problem
Testing complex VLSI circuits for faults becomes increasingly difficult due to inaccessibility of internal elements and interdependencies, with existing methods requiring significant resources and often failing to achieve close to 100% fault detection, especially with pseudo-random pattern generation methods that are costly and inefficient.
Innovation Solution
A built-in self-test (BIST) circuit that dynamically selects weights for test patterns using weight select logic between scan chains and a pseudo-random pattern generator, allowing for high fault coverage with minimal hardware overhead by switching between candidate test patterns on a per-scan-cell basis and using a decompressor with a pre-determined seed value to maximize fault coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If pseudo-random pattern generation is used for BIST, then hardware complexity is reduced, but fault detection capability deteriorates
Solution Approach 1:
The patent implements dynamic weight selection for test patterns, allowing the BIST circuit to adaptively change pattern weights during testing. This dynamic approach enables the simple pseudo-random generator to achieve better fault detection by selectively emphasizing certain pattern weights, resolving the contradiction between hardware simplicity and testing effectiveness.
Solution Approach 2:
The patent changes the parameter of pattern weights in the pseudo-random test generation. By introducing selectable weight configurations (e.g., uniform weight, alternating weight, random weight), the system enhances fault detection capability without increasing hardware complexity, as the weight selection is achieved through logical control rather than additional physical test generators.
2Reliability
If deterministic ATPG is used to achieve close to 100% fault detection, then resource requirements increase significantly
Solution Approach 1:
The patent uses pseudo-random patterns with selectable weights as a simpler, more resource-efficient alternative to deterministic ATPG. Instead of generating and storing extensive deterministic test sets, the system uses compact pseudo-random sequences that can be dynamically weighted to target specific fault types, significantly reducing memory and computational resources while maintaining acceptable fault detection levels.
Solution Approach 2:
By varying the weight parameters of pseudo-random patterns, the system achieves adaptive fault detection without requiring the extensive resources of deterministic ATPG. The weight selection allows the same hardware to effectively target different fault classes through parameter adjustment rather than through complex test pattern generation.
3Reliability
If weighted random testing is implemented to improve fault coverage, then logic overhead increases
Solution Approach 1:
The patent implements dynamic weight selection mechanisms that allow the BIST circuit to adaptively change pattern weights during testing. This dynamic approach enables the system to achieve better fault coverage by selectively emphasizing certain pattern weights, resolving the contradiction between testing effectiveness and hardware overhead through time-multiplexed weight application.
Solution Approach 2:
The patent creates a universal weight selection logic that can generate multiple weight configurations (uniform, alternating, random, and custom weights) using a single hardware structure. This multi-functional approach allows the system to achieve comprehensive fault coverage across different fault types without proportionally increasing logic overhead, as the same hardware infrastructure serves multiple testing purposes.
Data Source
AI summary
A built-in self-test (BIST) circuit is disclosed that allows high fault coverage. Additionally, a method is disclosed for implementing the BIST circuit. In one aspect, the BIST circuit includes a plurality of scan chains that receive test patterns used in testing the integrated circuit. A pseudo random pattern generator provides test patterns to the scan chains. Weight select logic is positioned between the scan chains and the pseudo random pattern generator and controls the weightings of the test patterns that are loaded in the scan chains. In another aspect, the weight select logic can switch the weightings of the test patterns on a per-scan-cell basis. Thus, as the scan chains are loading, the weight select logic can effectively switch between test patterns being loaded into the scan chains.