Bistable RRAM With Stacked Memory Layers
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Solution Overview
Problem
The challenge in manufacturing high-density memory devices lies in achieving small dimensions and tight process variations for phase change memory materials, particularly in reducing the magnitude of the reset current required for phase change from crystalline to amorphous states, while maintaining reliable multi-bit storage capabilities.
Innovation Solution
A bistable resistance random access memory (RRAM) design utilizing multiple memory layer stacks, where each memory cell comprises conductive layers over programmable resistance random access memory layers, allowing for multilevel memory states and reduced resistance variations, achieved through specific etching and dielectric spacer techniques to control resistance values and achieve desired logic states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the size of the phase change material element and contact area are reduced, then the reset current magnitude is reduced, but the manufacturing precision and process control become more difficult
Solution Approach 1:
The memory device is divided into multiple memory layers with multiple phase change material elements arranged in a three-dimensional stack. Each layer can be independently controlled and addressed, allowing the system to achieve high density without requiring extremely small individual element sizes. The segmentation into multiple layers with different contact areas enables differential resistance control while maintaining manufacturable dimensions.
Solution Approach 2:
The patent transitions from a two-dimensional planar memory structure to a three-dimensional stacked architecture. Multiple memory layers are vertically stacked with intermediate conductive layers, creating a multi-layered structure that increases storage density without proportionally reducing the contact area of individual elements. This dimensional change allows maintaining larger contact areas for manufacturability while achieving high density through vertical stacking.
2Quantity of substance
If multiple memory layers are stacked to increase density, then the memory capacity is improved, but the resistance variations between layers increase
Solution Approach 1:
Different memory layers are designed with different contact areas to create distinct resistance characteristics. The first memory layer has a first contact area and the second memory layer has a second contact area, creating locally optimized structures. This local quality differentiation allows each layer to contribute differently to the overall resistance, enabling multilevel memory states while the cumulative effect across layers provides density improvement. The varying contact areas compensate for resistance variations by design rather than requiring uniformity.
Solution Approach 2:
The patent systematically varies the contact area parameter across different memory layers. The first phase change material element has a first contact area and the second phase change material element has a second contact area, creating a gradient or stepped structure. This parameter change strategy allows controlling the resistance contribution of each layer, enabling the system to achieve desired resistance ratios for multilevel storage while managing variations through deliberate design rather than requiring tight process control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances memory density, reduces resistance variations, and enables efficient multi-bit storage by leveraging the resistance differences between layers to achieve four logic states per memory cell, thereby improving the overall performance of phase change memory devices.
Implementation Method 1
Phase change based memory materials, like chalcogenide based materials and similar materials, can also be caused to change phase by application of electrical current at levels suitable for implementation in integrated circuits. The generally amorphous state is characterized by higher resistivity than the generally crystalline state
Implementation Method 2
The change from crystalline to amorphous, referred to as reset herein, is generally a higher current operation, which includes a short high current density pulse to melt or breakdown the crystalline structure
Data Source
AI summary
A method is described for operating a bistable resistance random access memory having two memory layer stacks that are aligned in series is disclosed. The bistable resistance random access memory comprises two memory layer stacks per memory cell, the bistable resistance random access memory operates in four logic states, a logic “00” state, a logic “01” state, a logic “10” state and a logic “11” state. The relationship between the four different logic states can be represented mathematically by the two variables n and f and a resistance R. The logic “0” state is represented by a mathematical expression (1+f)R. The logic “1” state is represented by a mathematical expression (n+f)R. The logic “2” state is represented by a mathematical expression (1+nf)R. The logic “3” state is represented by a mathematical expression n(1+f)R.