Nanoinformatics TRIZ Cases

Resistor-like junctions and parity-check lines enhance fault tolerance in nanowire crossbars despite high defect rates.

Segmenting the absorber film into distinct layers resolves inspection contrast issues while maintaining high-resolution pattern formation.

Varying inner spacer thicknesses tunes SRAM cell threshold voltages to reduce write minimum voltage.

Segments convex integer quadratic programming problems into fundamental cubes and applies penalty terms to enable solution via binary optimizers.

A Ni3Si gate electrode layer introduces strain into suspended semiconductor channel material nanosheets within nFET structures.

Real-time feedback control of contact line velocity reduces overlay distortions during polymerizable material imprinting.

Thermal oxidation diffuses germanium into mandrels to form silicon germanium fins, reducing spacing requirements and improving epitaxial growth selectivity.

A double gate planar field effect transistor uses vertically stacked nanowires with a self-aligned gate conductor.

Structured metallization antenna surrounds nanorods to increase spontaneous emission rates, reducing switching times and optical power droop.

Inner spacers guide gate material filling in GAA semiconductor structures, reducing defects from narrow trench complexity.

Multiple masking steps create patterned magnetic media with offset data and servo regions, reducing adjacent bit interference.

A nanowire transistor with a surrounding gate structure controls the channel from all directions.

Applying controlled back surface pressure during template separation prevents resist pull-out defects caused by adhesion variations.

A conductive layer contacts the substrate and nanowire periphery, reducing interface resistance and electrical losses in optoelectronic structures.

Selective trimming of dielectric fins reduces residual sacrificial cladding, enabling sufficient inner spacer thickness to prevent gate-source shorts.

Sidewall epitaxial growth creates nanotube vertical MOSFETs that reduce parasitic capacitance and enhance switching speed.

A reflective photomask blank uses a zirconium silicon oxide protection film to shield the multilayer reflection film during absorber layer patterning.

Thicker non-magnetic layer on topography minimizes magnetic flux interference in bit patterned media trenches.

An imprint apparatus controller compares resin images to a reference state for real-time quality assessment.

A vertical diode structure utilizes opposite substrate surfaces to form a large p-n junction area within thin semiconductor layers.

Porous VOx thin films accumulate charge density to resolve the contradiction between ion storage capacity and optical transmissivity.

A photo-curable organic material imprint system adjusts template pressing force based on measured residual film thickness to ensure precise pattern alignment.

A lattice-patterned reticle masks etching to form pillar arrays, narrowing gaps with a second material to resolve packing density limits.

Integrating a resonant tunneling transistor with a wire unit eliminates external amplifiers and enables dynamic frequency tuning via gate voltage.

A partial buried insulator layer beneath source or drain regions separates vertical nano-sheets to increase the beta ratio and improve SRAM read margins.

Tin-doped chromium hard mask films increase chlorine dry etching rates to shorten processing time and reduce resist damage during mold production.

A photoactive layer uses a third material to control donor-acceptor crystallization.

An imprinting apparatus interpolates uncured resin application distribution across multiple substrate shots using relative position variables.

Carbon nanotube lower electrodes withstand high current density at narrow interfaces, reducing power consumption and eliminating damascene process complexity.

A semiconductor structure with a recessed source/drain region and a wider metal contact portion disposed within the recess to reduce parasitic capacitance.

A vertical gate all-around device introduces lateral strain into the channel structure using gap-filling materials to enhance charge carrier mobility.

Stacked memory layers with varying contact areas reduce resistance variations and enable multilevel storage without tight process control.

Segmented gas outlets dynamically target the interstice between mold and substrate, preventing unfilled pattern portions without enlarging the substrate stage.

A fluorescent organic electroluminescent device employs a host-dopant emitting layer and an adjacent blocking layer to confine triplet excitons.

Directed self-assembly materials pattern vertical nanowire transistor channels within guide openings.

A hybrid polymer mold uses semi-fluorinated molecules to form a low-surface-energy layer on the template surface.

A plasmonic transistor uses a gate-controlled cluster to switch optical properties within a nanoscale gap.

Direct mechanical pattern transfer eliminates optical alignment errors while angled sidewalls improve conductive material filling.

A CMOS structure uses identical channel conductivity and gate work functions to simplify FinFET and GAA fabrication.

Ionized gas nozzles remove static charges from molds during transfer, preventing dust adhesion and maintaining throughput.

A vertical field effect transistor uses an unshielded organic semiconductor layer in direct contact with a dielectric to enhance charge carrier mobility.

Ion implantation compensates strain in relaxed buffer layers, preventing wafer bowing while maintaining high carrier mobility.

Adjust patterning device features to compensate for effective shadow angles, reducing displacement and dimension errors in pattern transfer.

Low-temperature plasma nitridation prevents channel deformation in germanium and silicon-germanium transistors by maintaining surface roughness below 1.0nm RMS.

A photoactive device uses a donor-acceptor heterojunction to dissociate excitons into free charges.

An intermediary sensitizing layer extends spectral response into the near-infrared region without impeding charge carrier transport efficiency.

Nanodots with lower band gap energy in a composite charge trap layer improve program speed and retention while reducing operating voltage.

A nanowire phase change memory device uses a p-n junction to thermally switch material states.