Double Gate Planar FETs Vertical Stacking
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Solution Overview
Problem
Current semiconductor nanowire field effect transistors face challenges in achieving high layout density and current carrying capacity due to small diameters, which are beyond the capabilities of optical lithography, and struggle to integrate with other chip structures effectively.
Innovation Solution
The solution involves vertically stacking nanowires and planar layers with a self-aligned gate-to-landing pad structure, allowing for the creation of small-diameter nanowires in a vertical mesh and planar double-sided FETs, using chemical etching and sacrificial material removal to increase channel width layout density and reduce threshold voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If nanowire diameter is reduced to increase layout density, then channel width density improves, but current carrying capacity deteriorates
Solution Approach 1:
The patent transitions from one-dimensional lateral scaling to three-dimensional vertical stacking. Multiple nanowires are stacked vertically to achieve high channel width density without reducing individual nanowire diameter, thereby maintaining current carrying capacity while increasing overall device density beyond optical lithography limits
Solution Approach 2:
The patent implements gate structures that completely surround each nanowire in a nested configuration. The gate conductor envelops the channel material, creating a wrap-around gate that provides superior electrostatic control while maintaining compact device footprint
2Quantity of substance
If nanowire diameter is reduced to match channel width density of planar devices, then layout pitch decreases, but manufacturing capability deteriorates
Solution Approach 1:
The patent uses vertical stacking to achieve high channel width density without requiring sub-32nm lateral pitch. By stacking multiple nanowires vertically, the effective channel width increases while the lateral footprint remains compatible with current optical lithography capabilities
Solution Approach 2:
The patent employs preliminary self-aligned formation of nanowire stacks and gate structures. The gate material is deposited conformally around the nanowires before final patterning, ensuring precise alignment without requiring additional lithography steps at the nanowire scale
3Device complexity
If conventional nanowire fabrication is used, then device simplicity is maintained, but integration with other chip structures deteriorates
Solution Approach 1:
The patent creates a universal stacked nanowire platform that can be integrated with both planar devices and other nanowire structures on the same chip. The self-aligned gate-to-landing pad formation and standardized stack architecture enable seamless integration across different device types while maintaining fabrication simplicity
Data Source
AI summary
A transistor device includes multiple planar layers of channel material connecting a source region and a drain region, where the planar layers are formed in a stack of layers of a channel material; and a gate conductor formed around and between the planar layers of channel material.